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TMS320F28384D: Power Sequencing and XRSn

Euan T
Prodigy 40 points

Part Number: TMS320F28384D

Tool/software:

Hello,

I have a question in relation to the power sequencing section text shown below:


7.10.1.4.2 Signal Pins Power Sequence
Before powering the device, no voltage larger than 0.3 V above VDDIO or 0.3 V below VSS should be applied to any digital pin; and no voltage larger than 0.3 V above VDDA or 0.3 V below VSSA should be applied to any analog pin (including VREFHI and VDAC). Simply, the signal pins should only be driven after XRSn goes high, provided all the 3.3-V rails are tied together. This sequencing is still required even if VDDIO and VDDA are not tied together.


I am following the power of sequence of bringing up the VDDIO(3.3V) and then the VDD(1.2V),however I would like to clarify if not allowing voltage to be applied to the GPIO pins before XRSN goes high excludes the Boot mode GPIO pins (72 and 84)? Or do the boot mode pins required a different 3V3 source to apply voltage after the XRSN goes high?


Thanks

  • +1
    TI__Mastermind 36526 points

    Hi,

    Euan T said:
    Simply, the signal pins should only be driven after XRSn goes high, provided all the 3.3-V rails are tied together. This sequencing is still required even if VDDIO and VDDA are not tied together.

    I think that this is being very cautious.

    Euan T said:
    Before powering the device, no voltage larger than 0.3 V above VDDIO or 0.3 V below VSS should be applied to any digital pin; and no voltage larger than 0.3 V above VDDA or 0.3 V below VSSA should be applied to any analog pin (including VREFHI and VDAC).

    This is the guidance that should be followed. As long as the boot pins are not higher than 0.3V above VDDIO, you will be ok. 

    Best Regards,

    Ben Collier