TMS320F28377D: Could you please explain why the OST bit of the TZFLG is set, but the TZOSTFLG does not go High?

Hi Allison,

Thank you for your reply,

This problem was not solved.

The TZOSTFLG is set and both flags are cleared.
In this case, the TZOSTFLG is set even when the TZOSTFLG is not set.
Therefore, both flags cannot be cleared.
Can you tell me why the TZOSTFLG is set but the TZOSTFLG does not stand ?

Best Regards,

Ito

Hi Ito,

Allison is currently out of office but will have a response back to you when she returns at the end of the week.

Best Regards,

Delaney

Hi Ito,

Thanks for your patience. Can you confirm that you are clearing the flags when the trip condition is no longer present per the TRM note? 

Best Regards,

Allison

Hi Allison,

Thank you for your reply.

The GPIO value to be tripped is cleared after confirming that the tripping condition has ended.

In addition, the above description states that if this condition is not observed,
an OST interrupt will occur while theOST flag remains Low, but in this situation,
the OST flag is up, but the flag in the TZOSTFLG register is not up.

Best regards,

Ito

Ito,

The expert is currently out of office and will respond to your query when they return next week.

Best Regards,

Aishwarya

Hi Ito,

Thanks for your patience while I was out. Can you please send me your trip zone initializations?

Best Regards,

Allison

Hi Allison,

Thank you for your help.

Some of the code was shared with us by may customer.

f28375d.h

    PWM1_TZSEL |= OSHT1_SELECT_BIT;

    PWM1_TZCTL |= TZA_LOW_BIT + TZB_LOW_BIT;


    PWM1_TZCLR = 0x007F;

    PWM1_TZOSTCLR = 0x00FF;

    PWM1_TZFRC = FF_OST_BIT;

Best Regards,

Ito

Hello Ito,

Can you clarify how and when the customer is checking these register values? Is this in some interrupt/poll or through debug window?

Is the customer able to send a small isolated test case so I can try this on my end?

Best Regards,

Allison

HI Allison,

Thank youfor your reply.

We only want to know when to set and clear the flags in the TRM TZOSTFLG register.
We do not need to check the operation.
When the OST bit of TZFLG stands but TZOSTFLG does not, what are the possible phenomena or conditions?

I do not understand the description of OST1 in the TRM.

According to this, the latch status can be checked by the OST if the OST flag in the TZFLG register is set.

Allison Nguyen said:

Can you clarify how and when the customer is checking these register values?

When a TZ occurs, an interrupt is triggered, and detect anomaly.
Within the interrupt, we are monitoring the OST1 bit of the PWM1_TZOSTFLG register, but occasionally this bit does not go High.
However, the INT and OST bits of the PWM1_TZFLG register do go High, causing only the trip to occur without anomaly detection.
At this time, none of the other bits in the PWM1_TZOSTFLG register are set, and the entire register is zero.

Best Regards,

Ito

Hi Ito,

Please allow another day or 2 for me to form my response. In the meantime, out of curiosity (this may be unrelated), what are the PWM clock dividers being used?

Best Regards,

Allison

Hi Allison,

Thank you for your help.

I use this divider.

Best Regards,

Ito

Hi Ito, 

Apologies let me clarify- what values are you using for your EPWM CLKDIV and HSPCLKDIV dividers (TBCTL register of EPWM module)?

Best Regards,

Allison

Hi Allison,

Please answer the following questions first.
These question does not relate to our design, but asks about the general design approach.

When are the flags in the TZOSTFLG register set and cleared?
When the OST bit of TZFLG stands but TZOSTFLG does not, what are the possible phenomena or conditions?
I do not understand the description of OST1 in the TRM.

According to this, the latch status can be checked by the OST if the OST flag in the TZFLG register is set.
Are there any reference materials available?

Sorry Allison, but customers are rushing for answers.

If they need to investigate the clock divider, they need to explain why.

Best Regards,

Ito

Hello,

I have not seen this phenomenon in any past cases, so I need a test case to be able to run this. Can you please send all the EPWM configurations for me to do so?

Best Regards,

Allison

Hi Allison,

Thank you for your reply.

If my customer asks us to check the operation of this case, we will send you a test case.
Ignore this issue for this moment.
First, tell me about the TZOSTFLG register.

Sorry, please answer the following questions

K.Z said:

When are the flags in the TZOSTFLG register set and cleared?

Please tell us where in the TRM it is written correctly.
The customer wants to know the set and clear timing truth of the TZOSTFLG.
A test case should not be needed for this.
According to the description below, it appears that if the OST flag in the TZFLG register is set, it is just latched, is this true?

Tell me what is correct about the relationship between TZOSTFLG, TZFLG, OST1 and OST.

Best Regards,

Ito