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TMS320F28379D: 200Mhz Sysclk and Flash

Prakhar Gupta
Prodigy 70 points

Part Number: TMS320F28379D

Tool/software:

Hello.


I have a system that relies on a clockspeed double that of the Launchpad. This is the configuration I added to the device.h file

```

//
//
// 20MHz External oscillator. For use with SysCtl_getClock().
//
#define DEVICE_OSCSRC_FREQ          20000000U

//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// PLLSYSCLK = 400MHz = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2)
//
#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) |  \
                                     SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) |   \
                                     SYSCTL_PLL_ENABLE)

//
// Define to pass to SysCtl_setLowSpeedClock().
// Low Speed Clock (LSPCLK) = 400 MHz / 2 = 200 MHz
//
#define DEVICE_LSPCLK_CFG           SYSCTL_LSPCLK_PRESCALE_2

//
// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the
// code below if a different clock configuration is used!
//
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2)

#define DEVICE_LSPCLK_FREQ          (DEVICE_SYSCLK_FREQ / 2)
```


The programs I run on the system work great when I run off of RAM. However, when I attempted to move to a FLASH based config, I hit an ESTOP in Device Init. I have verified that my memory configuration is correct - as I can run the program correctly with FLASH using default sysclock. Conversely, I am able to run with the faster clock with a RAM configuration. 

The error during the call to Device_init() after calling Flash_initModule, and then Device_enableAllPeripherals. The address of the ESTOP is 0x3FE493. Very simiilar to TMS320F28379D: TMS320F28379D Flash memory programming: code breaks at ETRAP0 within InitFlash() - C2000 microcontrollers forum - C2000Tm︎ microcontrollers - TI E2E support forums, however i encounter this onlywhen i change the clock info from default to 200mhz

i am not sure how to proceed with resolving this.


Best
P
  • 0
    TI__Mastermind 18406 points

    Hi Prakhar,

    Max Sysclk frequency for this device is 200Mhz, why are you running at 400Mhz?

    Please make sure your min max follows the below guidelines in datasheet.

    Thanks

  • 0 in reply to Prarthan Bhatt
    Prodigy 70 points

    Hello Prarthan,

    I will double check clock configuration and get back to you with results. Why would this not cause issues with the RAM configuration?

  • 0 in reply to Prakhar Gupta
    Prodigy 70 points

    after adjusting the configuration of clocks to limit sysclk to 200 MHz as recommended, everything seems to boot correctly. I am really intrigued that the non-flash parts of the system supported the 400 mhz sysclk in RAM mode, espially EPWMCLK which would have been running at 200mhz formerly. 

    I suspect that this can continue to work in FLASH configuration if the number of wait states were to be increased considerably beyond the minimum of 3. 


    If I understand correctly, the Counters of the CLB run in sync with EpWMCLK for the corresponding CLB. If EPWMCLK were to half, in order to maintain the same temporal behavior, the counter matches should also be halved as well - yes?

    Thank you

  • +1 in reply to Prakhar Gupta
    TI__Mastermind 18406 points

    Hi,

    Even if it ran at 400Mhz doesnt mean it supported that sysclk in RAM mode. Chip is designed to support max 200Mhz sysclk only keeping limitations in mind hence we don't recommend to ever exceed the datasheet limits.

    Prakhar Gupta said:
    If I understand correctly, the Counters of the CLB run in sync with EpWMCLK for the corresponding CLB. If EPWMCLK were to half, in order to maintain the same temporal behavior, the counter matches should also be halved as well - yes?

    Please make another thread if you have more questions on CLB clocking

    Thanks