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TMS320F28375S: Power sequence

Oba
Genius 17945 points

Part Number: TMS320F28375S

Tool/software:

Hello,

 

My customer has some questions for F28375S power sequence.

 

1.

The datasheet says that during the ramp, VDD should be kept no more than 0.3V above VDDIO at 6.9.1.3 VDD Requirements on P60.

Does it apply to not only power-up but also power-down?

 

2

It also says that before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no

voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI) at 6.9.1.1 on the same page.

 

Does it apply to during power-down sequence?

For example, if VDDREFHI is higher voltage than VDDA and VDD in a short time during power-down sequence, could it damage the device?

 

Regards,

Satoshi Obata

  • +1
    TI__Expert 6610 points

    Hello,

    1. Yes, it applies during power-down as well. It would prevent latch-up and avoid excessive leakage currents that could damage the device.

    2. Same case for power-down sequence. if VDDREFHI is higher voltage than VDDA and VDD current could flow backwards through protection diodes or internal analog circuits and damage the device.