• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 133 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P659DK-Q1: MCAN Register Offset Discrepancy

Ryan Helminen
Prodigy 10 points
Part Number: TMS320F28P659DK-Q1
Other Parts Discussed in Thread: C2000WARE

Tool/software:

There seems to be a discrepancy between the MCAN register offsets between the reference manual and what is configured in the c2000ware core SDK.

As one example, the reference manual states that the MCAN_CCCR register is at offset 0xC in Table 35-30, but the c2000ware library file f28p65x\driverlib\inc\hw_mcanss.h puts it at offset 0x18.

I would tend to believe the header file because Table 35-30 increments the offsets by 2 even though the registers are 32 bits in size.

  • 0
    TI__Mastermind 39490 points

    Hi Ryan,

    The register offsets in the TRM are represented in the smallest C2000 (C28x) byte size, which is 16-bit wide.  This can be a bit confusing since a normal bye is 8 bits wide.  MCAN registers are 32 bits wide so the step offset as show in TRM is by 2.  In the SDK, addressing step was abstracted so it would 'follow' the 8-bit byte mode as with the rest of the world, hence the offset is expressed in terms of 32-bit step or 4 bytes as declared in hw_mcanss header.  The SDK uses macros HW_WR_FIELD32, HW_SET_FIELD32, HW_RD_FIELD32...etc to take care of this operation.

    Our latest C29 core-based devices is now able to address the smallest byte unit of 8 bits so the offsets of those products will be by 4 for 32-bit registers.

    Regards,

    Joseph