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Original question:

TMS320F28P659DK-Q1: CPU4 Periodic Software Read Back of Static Configuration Registers

TMS320F280049C-Q1: INC4 Safety Mechanisms - clarifications needed

Jens G
Expert 3545 points

Part Number: TMS320F280049C-Q1

Tool/software:

Hi TI team,

In the Safety Manual of the TMS320F28004x family, some generic safety mechanisms (SMs) are mentioned, applicable to several peripherals. “Periodic Software Read Back of Static Configuration Registers” SM seems to be applicable for INC (IDs - INC4).

Similar for CPU4 I was able to find it here, but its missing the INC4 portion.

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1387891/tms320f28p659dk-q1-cpu4-periodic-software-read-back-of-static-configuration-registers?tisearch=e2e-sitesearch&keymatch=Periodic%2520Software%2520Read%2520Back%2520of%2520Static%2520Configuration%2520Registers#

 Unfortunately I have not been able to identify “configuration” registers for this device partition.

Thanks

Jens

  • 0
    TI__Expert 7835 points

    Hi Jens,

    Here are some registers they may consider and evaluate if these registers are related to their safety goal.

    Transient/Permanent faults in configuration registers
    1. Secondary master selection (static, SECMSELx) logic selects wrong bus master
    2. Peripheral core selection(static, CPUSELx) logic selects wrong bus master
    3. Incorrect configuration register data (CPUSEL, SECMSEL) to be read/written resulting in incorrect transactions

  • 0 in reply to Han Zhang6
    Prodigy 10 points

    Hello Han,

    Jens created this thread on my behalf and I will follow-it up.

    I have not been able to find CPUSEL nor SECMSEL registers/register fields in any of the following documentation:

    - sprui33g.pdf:TMS320F28004x Real-Time Microcontrollers - Technical Reference Manual

    - spru430f.pdf: TMS320C28x CPU and Instruction Set - Reference Guide

    Are these described in any other document?

    Thank you,

       Nicos

  • 0 in reply to Nicos Zdukos
    TI__Expert 7835 points

    Hi Nicos,

    Please allow me to clarify on the registers. The original answer I used our internal name. Sorry about the confusion. 

    1. Secondary master selection (static, SECMSELx):  LSxMSEL Register (3.15.17.9 TRM)

    2. Peripheral core selection(static, CPUSELx): PERIPH_AC_REGS Registers (3.15.11 TRM)

    Han