TMS320F28386D: TMS320F2838x Peripheral Frames details

Alex,

Thanks for reaching out, I'll address each of your points below:

Alexy Torres said:

1) How are peripheral frames connected to the mains busses (Sys, DMA, CLA)?

At a high level, you can think of each peripheral frame as a local bus aggregator, that then connects to the respective hosts(CPU, DMA, CLA) as shown in the block diagram inside the DS that you mention

Alexy Torres said:

2) Are the peripheral frames capable of servicing multiple transactions at the same time?
3) If 2) answer is no, what arbitration mechanism is in place to arbitrate between the different bus?

No, for a given frame only one peripheral can be accessed at a time.  There are two exceptions to this, the ADC result and GSx SRAMs.

The arbitration details can be found across these chapters in the TRM:

Memory:

https://www.ti.com/document-viewer/lit/html/SPRUII0F#GUID-882DB8BE-0E22-4EF7-AC64-DFD2561B7889/TITLE-SPRUII0ACCESS_ARBITRATION 

CLA:

https://www.ti.com/document-viewer/lit/html/SPRUII0F#GUID-D8FF1BC2-90DF-424D-8AB9-C3213EF93C14/TITLE-SPRUHM8SPRUFB89952 

DMA:

https://www.ti.com/document-viewer/lit/html/SPRUII0F#GUID-D8FF1BC2-90DF-424D-8AB9-C3213EF93C14/TITLE-SPRUHM8SPRUFB89952

Alexy Torres said:

4) To which bus(es) is connected each peripheral frame? The Data sheet provides a diagram with connections but I would like to have more textual information about this.

This table in the DS should provide this information textually: https://www.ti.com/document-viewer/TMS320F28386D/datasheet#GUID-20210930-TA0T-5RHG-HZDS-GRJDGMDTZHWC/TITLE_A_TM_C28_ALLBASEADDRESSES_PRIPHERALF

Alexy Torres said:

5) Can two different bus (say CLA1 bus and CPU1 bus) access two different peripherals on two different peripheral frames at the same time?

This is correct, there is no restriction when different peripheral frames are involved.

Alexy Torres said:

More globally, is there a more detailed reference guide for peripheral frames for the TMS320F2838x family devices?
The Chapter 8.3 CLA, DMA, and CPU Arbitration or the TRM is not completely clear about those points.

I understand and agree with your point; something in the System Control Chapter would be appropriate I think, since not everyone will use DMA or CLA or know to look there.  Let me talk with some others and see what we can do to clear this up.

Best,

Matthew