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TMS320F28P650DK: Software diagnostic library implementation problems

Part Number: TMS320F28P650DK

Tool/software:

Hello, 

I am implementing SDL from driverlib 5.04.00.00 to my device and facing some implementation issues.

1.
STL_CPU_REG_checkCPURegisters(): program crashes when execute loopCPUReg2Test assembly function. (I am using only CPU1). For now I have uncommented that function from assembly code. Is it a correct solution or would you suggest better one?

2. 
STL_CPU_REG_checkVCRCRegisters(): I have taken a code snipset from your example - f28p65x_test_application_cpu1 where you are calculating CRC from the following array.

float32_t faUser_crcData[STA_USER_CRC_DATA_SIZE] =
    {0.00006104, 0.00164795, 0.00762939, 0.02093506,
     0.04449463, 0.08123779, 0.13409424, 0.20599365,
     0.29962158, 0.41204834, 0.53472900, 0.65887451,
     0.77569580, 0.87640381, 0.95220947, 0.99432373};

which is stored in memory as the following string:
029A 3880 0007 3AD8 FFF6 3BF9 8001 3CAB 4000 3D36 6000 3DA6 5000
3E09 F000 3E52 6800 3E99 F800 3ED2 E400 3F08 AC00 3F28 9400 3F46
5C00 3F60 C400 3F73 8C00 3F7E

Problem is that the result of CRC calculation inside of STL_CRC_checkCRC() does not mach with any result I got from online CRC calculator e.g. https://crccalc.com/. (actualy the results are differ whatever string I use). Could you please describe how particular bytes are processed or how to organize data to mach in other calculator? 

3. 
STL_CAN_RAM_checkErrorStatus(CANA_BASE):  occasionally returns STL_CAN_RAM_ERROR after applying the first testing pattern. What could be the problem?
I am using it in the following way

        #define CANMSGRAM_END              0x4C7FFUL 
       ...
        uint16_t uiTestResult;
        STL_CAN_RAM_testRAM(CANA_BASE, STL_MARCH_PATTERN_ONE, CANA_MSG_RAM_BASE, CANMSGRAM_END, STL_CAN_RAM_NO_COPY);
        uiTestResult = STL_CAN_RAM_checkErrorStatus(CANA_BASE);
        STL_CAN_RAM_testRAM(CANA_BASE, STL_MARCH_PATTERN_TWO, CANA_MSG_RAM_BASE, CANMSGRAM_END, STL_CAN_RAM_NO_COPY);
        uiTestResult |= STL_CAN_RAM_checkErrorStatus(CANA_BASE);
        STL_CAN_RAM_testRAM(CANA_BASE, STL_MARCH_PATTERN_THREE, CANA_MSG_RAM_BASE, CANMSGRAM_END, STL_CAN_RAM_NO_COPY);
        uiTestResult |= STL_CAN_RAM_checkErrorStatus(CANA_BASE);
        STL_CAN_RAM_testRAM(CANA_BASE, STL_MARCH_PATTERN_FOUR, CANA_MSG_RAM_BASE, CANMSGRAM_END, STL_CAN_RAM_NO_COPY);
        uiTestResult |= STL_CAN_RAM_checkErrorStatus(CANA_BASE);

4.
STL_HWBIST_runFull(STL_HWBIST_NO_ERROR): when debugging, the code crashes at line 388 in stl_hwbist_s.asm and it is invoked error message "Can't Single Step Target Program" / Can't Run Target CPU

  • May I ask which safety standard you're targeting?

    1. Are you disabling interrupts before calling the function? The loopCPUReg2Test section tests the CPU IER register, so if you haven't globally masked interrupts before calling the function, you might be getting an interrupt while the CPU registers are in a bad state, causing the application to crash.

    2. I had to use a different calculator that allowed me to change the init value and rearrange the bytes so the low byte comes before the high byte (not the way the memory browser presents them), but I was able to get a match:

    3. I've never seen that behavior before. Can you put a breakpoint in the STL_CAN_RAM_checkErrorStatus function and try looking at the CAN_PERR register for more info? It's only the STL_MARCH_PATTERN_ONE? If you change the order the patterns are used in, does it still fail with STL_MARCH_PATTERN_ONE or does it fail on whichever call to STL_CAN_RAM_testRAM is first?

    4. It's normal for HWBIST to disrupt the debugger connection. There's a "Debugging HWBIST In-System" section in this app note that gives some tips.

    Whitney

  • Hi Whitney, 
    Thank you for your reply.
    Problem no. 1,2,4 are resolved.

    Remaining problem is with CAN RAM check.

    Actualy, it doesn't metter which MARCH pattern is used as the first.  
    I have recorded a short video for reference. /cfs-file/__key/communityserver-discussions-components-files/171/CanMsgRamTestFault.mp4

    This test runs right after device initialization where are set sysclk and enabled clock to all peripherals. 
    I have found out that CAN_PERR is always set to 0x306 after the enabling clocks for CAN periphery and this value remains during the whole run time. 
    I gues it would explain why I am getting error after the first check, but don't know to resolve it. 

  • Is CAN_ES.PER also set after device init? Does running CAN RAM init (like CAN_initRAM) before trying the March tests help?

    Whitney

  • Hi Whitney,

    I have double checked the code and found out the CAN_initRAM() was missing. Now it is working.
    Thank you for your support.

    Jozef