TMS320F280039C: Questions about the epwm_ex3_synchronization routine.

Hi Zhen,

Thank you for your question. I believe that the first instance of the AQ event when TBCTR=0 for EPWM4 is missed due to the loading conditions happening when TBCTR=0.

Both TBPRD and CMPA/CMPB are set to load from shadow to active registers when TBCTR=0, and at the same time there is an AQ event for the EPWM output to go high when TBCTR=0. 

Can you please make the following change in the .syscfg file and let me know if the output is still the same?

Thanks & Best Regards,

Marlyn

Hi Marlyn,

Thanks for your reply, because I did not use syscfg tool, I added this condition in the code, which should be the configuration in your picture. But I still get the same waveform.

Hi Zhen,

Can you please change the shadow to active option for CMPA as well, try PRD?

Also, if possible, can you include the other EPWM outputs compared to EPWM1 in your scope capture? I would like to see if these follow the same pattern.

Best Regards,

Marlyn

Hi Marlyn,

Is that what you're saying?

    if(base!=EPWM1_BASE)
        EPWM_selectPeriodLoadEvent(base,EPWM_SHADOW_LOAD_MODE_SYNC);
    EPWM_setCounterCompareShadowLoadMode(base,
                                         EPWM_COUNTER_COMPARE_A,
                                         EPWM_COMP_LOAD_ON_SYNC_ONLY);

The following waveforms are obtained, ch1-ch4 being EPWM1A-EPWM4A respectively.

Hi Zhen,

Yes, something like what you have or the below. Does it change your output?

EPWM_setCounterCompareShadowLoadMode(myEPWM0_BASE, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD);

Hi Marlyn,

The problem with EPWM1A may be that I didn't connect the line properly, I see EPWM_selectPeriodDevent (myEPWM2_BASE/myEPWM3_BASE/myEPWM4_BASE, EPWM_SHADOW_LOAD_MODE_SYNC) is already in the routine.
Then the original routine general EPWM_setCounterCompareShadowLoadMode (base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO); Adjusted for EPWM_setCounterCompareShadowLoadMode (base, EPWM_COUNTER_COMPARE_A, EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD); But judging by the waveform, that doesn't seem to be the reason.

Hi Zhen,

Thank you for sharing the corrected screen-shot. Looks like a sync event is only issued on the rising edge of the TBCTR=0 signal. 

Can you please start TBCTR during initialization at a value slightly under TBPRD so that when you start your EPWM CLK, the counter has a chance to pass 0 and issue a sync event?

Best Regards,

Marlyn

Hi Marlyn,

Before enabling TBCLK=1, I set TBCTR of EMWM1 to 1900 and got the following waveform. I am not sure if this is what you said?

In addition, I have done several tests. First, I set the level of GPIO to 1 in EPWM1-ISR, and the following waveform is obtained. However, from the waveform, it can be seen that the first TBCTR=0 is not entered into ISR, but the second TBCTR=0.The waveform does agree with the actual test results, which generate interrupts and syncouts when TBCTR = 0. But why is interrupt and SYNCOUT generated only when TBCTR is 0 for the second time?

In addition, I made some Settings in IDLE loop of the program, when EPWM2-TBCTR>0, set GPIO to 1, and read that EWMP2-TBCTR is 376, EWPM2-TBPRD is 2000, and EPWM2-CMPA is 1000. From here, it seems that EPWM-TBCTR started counting and did not produce a corresponding action when equal to CMPA.

Hi Zhen,

Thank you for doing additional tests and sharing the results. Have you modified the phase shift values from what is shown in the example?

Zhen He said:

But why is interrupt and SYNCOUT generated only when TBCTR is 0 for the second time?

Let me replicate this issue on my setup. As I previously suggested, the EPWM could be looking for a transition edge of when TBCTR=0 for it to take the corresponding actions. I will need to discuss with some colleagues if this is case and what is happening here. I will get back to you as soon as possible. 

Best Regards,

Marlyn