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Original question:

TMS320F28P550SJ: ADC samples Read problem in TMS320F28P550SJ9 controller

TMS320F28P550SJ: ADC samples Read problem

Rakesh Bastawad
Prodigy 80 points
Part Number: TMS320F28P550SJ


Tool/software:

Dear team ,

I am doing this configurations for ADC i am facing issues in not getting proper counts on ADC RESULT REGISTER IF I AM GIVING 1.65 V TO ADC LINE I NEED GET 2048 COUNTS NUT ITS GIVING ME DIFFERENT VALUES ON VERY TIME I LOAD THE CODE TO CONTROLLER .

void ADC_Config(void)
{


shortcktignor[0] =0;
shortcktignor[1] =0;


EALLOW;


// Setup VREF as internal
//
SetVREF(ADC_ADCA, ADC_EXTERNAL, ADC_VREF3P3);
SetVREF(ADC_ADCC, ADC_EXTERNAL, ADC_VREF3P3);
//
// Set ADCCLK divider to /4
//
AdccRegs.ADCCTL2.bit.PRESCALE = 6;

//
// Set pulse positions to late EOC
//
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;

//
// Power up the ADC and then delay for 1 ms
//
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;


AdcaRegs.ADCCTL2.bit.PRESCALE = 6;

//
// Set pulse positions to late EOC
//
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;

//
// Power up the ADC and then delay for 1 ms
//
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
EDIS;

// DELAY_US(1000);


EALLOW;

AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0;
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 45; //cur0
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1;
AdcaRegs.ADCSOC1CTL.bit.ACQPS = 45; //cur0
AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2;
AdcaRegs.ADCSOC2CTL.bit.ACQPS = 45; //cur1
AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC3CTL.bit.CHSEL = 3;
AdcaRegs.ADCSOC3CTL.bit.ACQPS = 45; //cur8
AdcaRegs.ADCSOC3CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC4CTL.bit.CHSEL = 4;//cur9
AdcaRegs.ADCSOC4CTL.bit.ACQPS = 45;
AdcaRegs.ADCSOC4CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC5CTL.bit.CHSEL = 5; //dc_fb
AdcaRegs.ADCSOC5CTL.bit.ACQPS = 45; //Mtemp1
AdcaRegs.ADCSOC5CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC6CTL.bit.CHSEL = 6; //Mtemp1
AdcaRegs.ADCSOC6CTL.bit.ACQPS = 45;
AdcaRegs.ADCSOC6CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC7CTL.bit.CHSEL = 7; //Mtemp2
AdcaRegs.ADCSOC7CTL.bit.ACQPS = 45;
AdcaRegs.ADCSOC7CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC8CTL.bit.CHSEL = 8; //OVT_FB
AdcaRegs.ADCSOC8CTL.bit.ACQPS = 45;
AdcaRegs.ADCSOC8CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC9CTL.bit.CHSEL = 9; //ANA_1
AdcaRegs.ADCSOC9CTL.bit.ACQPS = 45;
AdcaRegs.ADCSOC9CTL.bit.TRIGSEL = 5;


// AdccRegs.ADCSOC6CTL.bit.CHSEL = 6; //ANA_2
// AdccRegs.ADCSOC6CTL.bit.ACQPS = 45; //IP_0
// AdccRegs.ADCSOC6CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC10CTL.bit.CHSEL = 10; //ANA_2
AdcaRegs.ADCSOC10CTL.bit.ACQPS = 45;
AdcaRegs.ADCSOC10CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC11CTL.bit.CHSEL = 11;
AdcaRegs.ADCSOC11CTL.bit.ACQPS = 45; //ANA_3
AdcaRegs.ADCSOC11CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCSOC12CTL.bit.CHSEL = 12;
AdcaRegs.ADCSOC12CTL.bit.ACQPS = 45; //ANA_4
AdcaRegs.ADCSOC12CTL.bit.TRIGSEL = 5;

// AdcaRegs.ADCSOC14CTL.bit.CHSEL = 14;
// AdcaRegs.ADCSOC14CTL.bit.ACQPS = 45; //IP_4
// AdcaRegs.ADCSOC14CTL.bit.TRIGSEL = 5;
//
// AdcaRegs.ADCSOC15CTL.bit.CHSEL = 15;
// AdcaRegs.ADCSOC15CTL.bit.ACQPS = 45; //IP_5
// AdcaRegs.ADCSOC15CTL.bit.TRIGSEL = 5;


//-------------IP CONFIG------------------
// AdccRegs.ADCSOC6CTL.bit.CHSEL = 0;
// AdccRegs.ADCSOC6CTL.bit.ACQPS = 45; //IP_0
// AdccRegs.ADCSOC6CTL.bit.TRIGSEL = 5;
//
// AdccRegs.ADCSOC10CTL.bit.CHSEL = 1;
// AdccRegs.ADCSOC10CTL.bit.ACQPS = 45; //IP_1
// AdccRegs.ADCSOC10CTL.bit.TRIGSEL = 5;
//
// AdccRegs.ADCSOC0CTL.bit.CHSEL = 2;
// AdccRegs.ADCSOC0CTL.bit.ACQPS = 45; //IP_2
// AdccRegs.ADCSOC0CTL.bit.TRIGSEL = 5;
//
// AdccRegs.ADCSOC1CTL.bit.CHSEL = 3;
// AdccRegs.ADCSOC1CTL.bit.ACQPS = 45; //IP_3
// AdccRegs.ADCSOC1CTL.bit.TRIGSEL = 5;
//
// AdccRegs.ADCSOC4CTL.bit.CHSEL = 4;
// AdccRegs.ADCSOC4CTL.bit.ACQPS = 45; //IP_4
// AdccRegs.ADCSOC4CTL.bit.TRIGSEL = 5;
//
// AdccRegs.ADCSOC7CTL.bit.CHSEL = 5;
// AdccRegs.ADCSOC7CTL.bit.ACQPS = 45; //IP_5
// AdccRegs.ADCSOC7CTL.bit.TRIGSEL = 5;

AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // End of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared

// AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // End of SOC0 will set INT1 flag
// AdccRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
// AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared

EDIS;

}

  • 0
    TI__Intellectual 2270 points

    Hi Rakesh,

    Can you please provide the below info to help understand the problem further: 

    • How is the ADC being triggered ?
    • What is the Difference in the ADC code that you are observing ?
    • Is it possible to share the ADC data reading part as well 

    BR,

    Nilesh

  • 0 in reply to Nilesh Khanna
    Prodigy 80 points

    hi Nilesh ,

    as the above details mentioned:

    1.ADC is triggered on EPWM interrupt.(AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = 5;)

    2.which are the pins are multi functions like ( analog and digital both for example : A2/B6/C9/CMP1_HP0/CAMP1_LP0/GPIO224/PGA1_INP) this pin has both functionality digital and analog but i set this pin as analog it is not giving proper analog counts as per the voltage given to the pin .

    3.i am reading data in EPwm interrupt through adc result register for EX: AdcaResultRegs.ADCRESULT2 ;

    regards,

    Rakesh

  • 0 in reply to Rakesh Bastawad
    TI__Intellectual 2270 points

    Hi Rakesh,

    Are you configuring the below register bits w.r.t the ADC input pin you are using, for below pin ?

    Rakesh Bastawad said:
    analog and digital both for example : A2/B6/C9/CMP1_HP0/CAMP1_LP0/GPIO224/PGA1_INP)

    Also need to configure below bit as well. 

    Please try the above and let me know if that helps. 

    BR,

    Nilesh