TMS320F28375D: How to continue supplying the SPI clock(SPICLK)

Hello,

First, I am concerned about the event being described. That does not sound like typical behavior for a peripheral device. Please clarify what undesired behavior is being observed after the CLK stops. Ideally, do this before moving on to my suggestion below- my suggestion is definitely a non-ideal workaround.

Note: Suggestion moved to secondary post due to length and, possibly an excess of detail. Apologies.

Regards,
Jason Osborn

(continued)

Second, there is no way to facilitate this based solely out of the SPI. My first thought was to use the CLB, as that would be an incredibly simple process, but unfortunately the indicated part number does not have one. One other way to duplicate this behavior that I can think of offhand is to utilize an ePWM output instead:

1. Verify that the pin being used for the SPI CLK also has an ePWM A or B output available. For example, is GPIO18 is being used for SPICLKA, the device TRM shows that this pin can also be used for the EPWM10A output signal.
   
   
2. Set up the relevant ePWM output using the following settings:
   
   1. XBAR settings
      1. Set an INPUTXBAR input to the GPIO being used for SPISTE. This input must be any of INPUTXBAR1-6
      2. Set an EPWMXBAR input to the chosen INPUTXBAR.
         
         
   2. ePWM basic settings
      1. Trip Zone Submodule
         1. Set one-shot trip to force GPIO low
         2. Force a one-shot trip in software for the duration of ePWM configuration to ensure GPIO remains in a known state
      2. Time-Base Submodule
         
         1. Up-Down-Count mode (for simplest configuration) 
         2. TBPRD -> PWM Frequency = SPI CLK frequency, based on LSPCLK and baud rate
         3. Enable TBCTL[PHSEN] to allow for sync-in signals to propagate
         4. Set TBCTL[PHSDIR] = 1b to count up after sync
      3. Action Qualifier Submodule 
         1. Up on CNT=ZRO
         2. Down on CNT=PRD
      4. AQ Submodule Sync settings (where 'x' is either ePWMA or ePWMB depending on selected pin)
         1. AQCTL[SHDWAQxMODE] = 1b
         2. AQCTL[LDAQxSYNC] = 10b
            1. Enable shadow loading
               
               
   3. ePWM settings to sync SPI and ePWM (where 'x' is either ePWMA or ePWMB depending on selected pin)
      1. Digital Compare Submodule
         1. Set the previously chosen EPWMXBAR signal as an input to DCx
            1. DCTRIPSEL[DCxHCOMPSEL] = chosen EPWM XBAR trip signal
               1. Sets DCxH to the trigger off of SPISTE, based on prev. XBAR settings
            2. TZDCSEL[DCxEVT1] = 000b
               1. When DCxH goes low, the DCxEVT1 trip signal is generated
            3. DCxCTL[EVT1SRCSEL] = 0b
            4. DCxCTL[EVT1FRCSYNCSEL] = 1b 
               1. No filter on the input signal
               2. Async signal
                  
                  
         2. Enable DCxEVT1 sync signal generation
            1. DCxCTL[EVT1SYNCE] = 1b
               
               
               
         3. Explicitly disable DCx force trip output
            1. TZCTL[DCxEVT1] = 11b --> no action
            2. TZCTL[DCxEVT2] = 11b --> no action
            3. TZCTLDCx = 0xFFF --> all actions disabled
3. Clear the one-shot trip from the ePWM. If all configurations are done correctly, then when SPISTE is set, the ePWM CLK will automatically synchronize.
   1. If a delay is desired based on SPI settings, change TBCTL[PHSDIR] to 0b and set the TBPHS register to the desired delay in ePWM clock cycles. Delay must be < TBPRD.
      
      
4. Warning: This will keep going indefinitely.
   1. To turn it off: (where 'x' is either ePWMA or ePWMB depending on selected pin)
      1. Set AQCTLx = 0x555
         1. Set the AQ to force the output low
      2. TBCTL[SWFSYNC] = 1b
         1. Force a one-time sync pulse
      3. Set AQCTLx = Up on CNT=ZRO, down on CNT=PRD
         
         
   2. This forces the output of the ePWM low until the next SPISTE pulse. After that pulse, the output will resume.

Apologies if this is a lot to take in- I like to be thorough. Essentially, this starts the ePWM clock when SPISTE is set, at which point it continues indefinitely, or until the user shuts it down by temporarily configuring the Action Qualifier with the Shadow Load mechanism.

Regards,
Jason Osborn

Sounds good. Please mark an answer as resolved when you have the chance.