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TMS320F28379D: Timing related queries for QDC in EQEP module

Prarambhik Sur
Prodigy 55 points

Part Number: TMS320F28379D

Tool/software: CCS

Hello,

I am implementing speed calculation and its related protections for my motor control project. The initialisation for my EQEP is as follows:

EQep1Regs.QDECCTL.bit.QSRC = 0; // Position-Counter Source Selection - Quadrature Count Mode
EQep1Regs.QEPCTL.bit.FREE_SOFT = 0; // Position Counter and Timer Capture Modules stop on emulation suspend
EQep1Regs.QEPCTL.bit.PCRM = 1; // Position Counter Reset on Maximum Position
EQep1Regs.QPOSMAX = 479; // Position Counter gets zero after 480 Positions(120 slots)
EQep1Regs.QEPCTL.bit.QPEN = 1; // Enable the eQEP Position Counter
EQep1Regs.QCAPCTL.bit.CEN = 1; // Enable eQEP Capture Module
EQep1Regs.QCAPCTL.bit.UPPS = 2; //5; // Unit event is set after 4 Clock Pulses
EQep1Regs.QCAPCTL.bit.CCPS = 7; // Capture Timer clock is prescaled by /128

I am getting correct speed. However I need to implement something that can detect whether both eqep A and B signals are coming or not. So if both the signals are proper I get UPEVNTS and QDC flags remain 0, is what my understanding is(Please correct me if I am wrong).
However, if any one of the signal comes like either A or B and the other is missing, then I will get an UPEVNT still(delayed as compared to healthy case) and QDC bit becomes high, is what my observation is.

I had a few queries related to these:

1. What is the logic inside the DSP which has been implemented to cause QDC to become high if one signal goes missing? How does it detect so?

2. The QDC flag remains high , if not cleared(even if the abnormal situation due to which it became high goes away). Why?

3. What is the timing of the QDC flag to become high. What i mean to say is, if I am removing one signal, the other one is still there, so at what instant of time does the DSP take the action of making QDC flag high. Is it based on QCLK or UPEVNT or what is the time instant?

4. Does the QDC flag becoming high has anything to do with what speed the motor is rotating currently at? I feel and observe that at higher speeds I get QDC flag appearance very frequently as opposed to lower speeds, where I get QDC high after quite some time( Please Note that once I get a QDC high, I am clearing it  as because it doesnt clear by itself. So the appearance of the next QDC is what I am asking about.) 

5. What is the major difference between QDC and QDF flag. What is the purpose for each of them?

Kindly note that the speed calculation which I do in the software is not based on delta X/T or X/delta T as mentioned in Manual.

It will be very much helpful for my project, if anyone could answer  and clarify on the same.

Regards,

Prarambhik

  • 0
    TI__Mastermind 27736 points

    Hi Prarambhik,

    1. The logic inside the DSP to cause the QDC (Quadrature Direction Change) flag to become high when one signal goes missing is based on the quadrature decoder state machine. The quadrature decoder expects the QEPA and QEPB signals to be 90 degrees out of phase. If one signal is missing or there is an invalid state transition (like both QEPA and QEPB changing at the same time), it is detected as a direction change, and the QDC flag is set.

    2. The QDC flag remains high until it is explicitly cleared by software because it is a sticky flag. It indicates that an invalid state transition or direction change has occurred, and the flag remains set until the software clears it, even if the abnormal situation goes away.

    3. The timing of the QDC flag becoming high depends on when the invalid state transition or direction change is detected by the quadrature decoder state machine. This can happen on any QCLK (quadrature clock) edge, as the quadrature decoder logic operates on each QCLK edge.

    4. The appearance of the QDC flag can be related to the motor's rotational speed. At higher speeds, the QCLK frequency is higher, and any glitches or missing pulses on the QEPA or QEPB signals are more likely to be detected as invalid state transitions, leading to more frequent QDC flag appearances. At lower speeds, the QCLK frequency is lower, and the quadrature decoder may be more tolerant of minor glitches or missing pulses before detecting an invalid state transition.

    5. The QDC (Quadrature Direction Change) and QDF (Quadrature Direction) flags serve different purposes:
    - QDC indicates that an invalid state transition or direction change has occurred in the quadrature decoder state machine, which may indicate a problem with the QEPA or QEPB signals.
    - QDF indicates the current direction of rotation detected by the quadrature decoder, based on the phase relationship between QEPA and QEPB signals.

    Regarding your speed calculation method, if you are not using the delta X/T or X/delta T methods mentioned in the manual, you may be using a different approach based on the QCLK frequency or some other method. The QDC flag can still be useful for detecting issues with the quadrature signals, regardless of the specific speed calculation method you are using.

    Best,

    Ryan Ma