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TMS320F28377D: Both synchronous and asynchronous interfaces for EMIF using the 28377D

albert qiu
Intellectual 340 points

Part Number: TMS320F28377D
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

CS0, CS2, CS3, CS4 of EMIF1 are used. When I use the sysconfig tool to configure, this tool shows that CS0 can only be used for synchronous interfaces, and CS2,3,4 can be used for asynchronous interfaces.

 If these 4 chips are selected at the same time, the address line MSB of CS0 supports A12 at most, and the pin of the original A13 is reused as CAS.

In this case, CS2,3,4 A13 will not be used, and CS0 will limit the maximum access address of CS2,3,4 to A12.

On the premise of using 4 CS at the same time, how should I set it so that the address line of CS2, 3, and 4 can reach 16 bits?

  • 0
    TI__Guru**** 200926 points
    albert qiu said:
    this tool shows that CS0 can only be used for synchronous interfaces, and CS2,3,4 can be used for asynchronous interfaces.

    You are correct. CS0 can only be used for synchronous memory, and CS2/3/4 can be used for async memories.

    When interfacing with synchronous memory, the maximum address signal is A12 since A13/CAS and A14/RAS are used as column/row address strobes. 

    albert qiu said:
    In this case, CS2,3,4 A13 will not be used, and CS0 will limit the maximum access address of CS2,3,4 to A12.

    CS0, CS2, CS3, and CS4 can not be active at the same time. There is no issue to use A12 as an address pin for CS2, CS3, and CS4. 

    albert qiu said:
    On the premise of using 4 CS at the same time, how should I set it so that the address line of CS2, 3, and 4 can reach 16 bits?

    Only one chip-select can be asserted (active LOW) at a time.