F29H85X-SOM-EVM: F29H85X-SOM-EVM

Hi  Aishwarya, 

 in your example you use only RTDMA2.  In  my code  I try  to use  RTMA1 on cpu1 and RTDMA2   in cpu2.  Is it possible to share my code with you ?

Regards

Youcef Bouchebaba

Hi Aishwarya

When I run the code, I get the following  error  :

C29xx_CPU1: Error during Flash Programming. Address 0x1000101C, FMSTAT (STATCMD on some devices) 0x00000000 , Value 0x00000101
C29xx_CPU1: Please make sure the memory location you are programming have not already been programmed.
C29xx_CPU1: Error during Flash Programming. Address 0x1000683C, FMSTAT (STATCMD on some devices) 0x00000000 , Value 0x00000101
C29xx_CPU1: Please make sure the memory location you are programming have not already been programmed.

Regards

Youcef

Youcef,

Apologies, there was a memory allocator tool change in the SDK that will be reflected in the GitHub by early next week. Please let me know on Monday/Tuesday, if you can run the example using the latest SDK. In the meantime, you can copy over the RTDMA1 code and comment out the RTDMA2 code in your imported project and that should work (just tested it).

Best Regards,

Aishwarya

Hi Aishwarya

 The rtdma example works  with the new sdk, However, I have  the following questions

(1)  The CPU1_SRAM_DATA is set to CDATA? How to changed to LD ?  The  same question for CPU2_SRAM_DATA is set to LDATA.

(2) It  seems   that RTDMA2  it is enabled  only when the CPU1  is  running, if CPU1 is stoped, the RTDMA2 doesn't work?

(3)  It seems that  we  can  not execute several starts  of the RTDMA  in the following  way :

       DMA_startChannel(myRTDMA2Ch0_BASE);

        done=0
        while(!done)
       {
           DMA_forceTrigger(myRTDMA2Ch0_BASE);
           SysCtl_delay(10);
         }

        done = 0

        DMA_startChannel(myRTDMA2Ch0_BASE);

        while(!done)
       {
           DMA_forceTrigger(myRTDMA2Ch0_BASE);
           SysCtl_delay(10);
       }

4  I think the mutli core rdma  example won't  work if the .txt is mapped to SRAM  program

Regards

Youcef Bouchebaba

Youcef,

youcef bouchebaba said:

(1)  The CPU1_SRAM_DATA is set to CDATA? How to changed to LD ?  The  same question for CPU2_SRAM_DATA is set to LDATA.

At this point, the tool automatically selects SRAM essentially based on which memory is available. I will loop in the tool owners to relay feedback and ask if there is any flexibility. You can copy and disable the SysConfig generated linker command files into a manual one and make modifications as needed.

youcef bouchebaba said:

(2) It  seems   that RTDMA2  it is enabled  only when the CPU1  is  running, if CPU1 is stoped, the RTDMA2 doesn't work?

Do you mean when CPU1 is halted, CPU2 is halted too and the RTDMA2 doesn't work? I believe RTDMA2 global and MPU settings are configured by CPU1 application, so when the two cores are out of sync (ie. CPU2 is reset but not CPU1, etc.) there could be an issue, but not sure what the case is here exactly.

youcef bouchebaba said:

(3)  It seems that  we  can  not execute several starts  of the RTDMA  in the following  way :

       DMA_startChannel(myRTDMA2Ch0_BASE);

        done=0
        while(!done)
       {
           DMA_forceTrigger(myRTDMA2Ch0_BASE);
           SysCtl_delay(10);
         }

        done = 0

        DMA_startChannel(myRTDMA2Ch0_BASE);

        while(!done)
       {
           DMA_forceTrigger(myRTDMA2Ch0_BASE);
           SysCtl_delay(10);
       }

What is the issue you are seeing? Does the channel not restart since it was disabled at the end of the previous operations? 

youcef bouchebaba said:

4  I think the mutli core rdma  example won't  work if the .txt is mapped to SRAM  program

The CPU1 application code is mapped to FLASH because it is executing from CPU1 FLASH. You can create specific output sections in the sections part of the memory allocator tool and specify where to load/run code from though. Is there a specific requirement to have the CPU1 .text file in SRAM?

Best Regards,

Aishwarya

Hi Aishwarya

(2)  When CPU1 is stopped and CPU2 is running, RTDMA2 does not receive the interrupt

(3) the channel does not restart even  if it is not deactivated at the end of the previous operation,

(4) When  I map all  the sections to SRAM (txt, bss, data..),   the CPUI goes into infinite loop when  the RTDMA2 starts its execution. 

Regards

Youcef

Apologies for the delay, please give me another day to get back to you.

Best Regards,

Aishwarya

Youcef,

I’m still reproducing the issue on my end. I will get back to you as soon as possible. Thank you. 

Best Regards,

Aishwarya

Youcef,

Thank you for your flexibility. Please see below.

youcef bouchebaba said:

(1)  The CPU1_SRAM_DATA is set to CDATA? How to changed to LD ?  The  same question for CPU2_SRAM_DATA is set to LDATA.

I've relayed the feedback to the SW team, and we will look into this feature for a future SDK release.

youcef bouchebaba said:

(2)  When CPU1 is stopped and CPU2 is running, RTDMA2 does not receive the interrupt

Where in CPU1 application code, is it stopped? Does this behavior change depending on where you stop it? RTDMA2 global and MPU settings are configured by RTDMA1, so if CPU1 is stopped before these configs, the RTDMA2 configs may not have taken place yet.

Some other possible issues are the CPUs are out of sync and/or there are issues with the clocking (though it probably isn't this).

youcef bouchebaba said:

(3) the channel does not restart even  if it is not deactivated at the end of the previous operation,

Reconfiguring the channels before starting them again should help fix this. 

youcef bouchebaba said:

(4) When  I map all  the sections to SRAM (txt, bss, data..),   the CPUI goes into infinite loop when  the RTDMA2 starts its execution. 

Ensure there are no linker command conflicts between CPU1 and CPU2 and the SRAM is properly initialized before executing code from it. You can provide code snippet if this doesn't resolve issue. Is there a specific issue you are mapping CPU1 to execute from RAM (the build configuration I provided was FLASH build BTW)

Best Regards,

Aishwarya

(2)  The CPU1 is stopped after  rtdma1 (cpu1) is started   (the RTDMA2 is already configured). The behavior don't change depending on where we stop it

(3) Even if reconfigure the channels before starting them don't fix this.

(4) I have  extended the led_ex2_blink_cpu1_cpu2_cpu3 to use rtdma1 on cpu1 and rdtma2 on cpu2 (or cpu3). There is no linker command conflicts . Is it possible to share the code with you ?

I have two others questions :

(a) I want to compare  F29H85X with TMS2838. In F29H85X, I use the following  optimization option paradigm/level  :   "0".   I want to known what is the equivalent optimization level on TMS2838  sdk :  optimization level = "0"  or = "off"  ?  and Speed vs  size=   "0"  or other "value" ?

b) It  seems  that I can not load both code  (.txt) of cpu1 and cpu3  to flash  memory.  I can load only the code  of  cpu1 to the flash, however the code  of cpu3 it can be loaded only to the RAM  ?

When I try to  run  led_ex2_blink_cpu1_cpu2_cpu3  as flash  configuration, I have the following  error :

            -  C29xx_CPU1: Trouble Writing Register PC_FORCE: (Error 0xFFFFFAAF)  or

             - This version of the flash plugin does not support loading applications from CPU3.  

Regards

Youcef Bouchebaba

Hi Aishwarya

I have Clarified the  questions  2, 3 and 4 . And I have two additional questions (a) and (b).

Best Regards

Youcef Bouchebaba

Hi Youcef,

Aishwarya is currently out of office. Please expect a delay in response until next week when she returns. 

Best Regards,

Delaney

Youcef,

youcef bouchebaba said:

(4) I have  extended the led_ex2_blink_cpu1_cpu2_cpu3 to use rtdma1 on cpu1 and rdtma2 on cpu2 (or cpu3). There is no linker command conflicts . Is it possible to share the code with you ?

Yes, please share it with me here or via private message, if needed. I will run it to observe the reported behavior.

youcef bouchebaba said:

(a) I want to compare  F29H85X with TMS2838. In F29H85X, I use the following  optimization option paradigm/level  :   "0".   I want to known what is the equivalent optimization level on TMS2838  sdk :  optimization level = "0"  or = "off"  ?  and Speed vs  size=   "0"  or other "value" ?

It is highly recommended, and the default, to use ‘-O1’ with F29x to truly take advantage of the C29x processor’s many benefits. Using ‘-O0’ will result in not great performance. There is no ‘equivalent’ optimization level because F29x is double the performance of F28x, at minimum . You can refer to the CPU and compiler related documentation on the F29x device page.

youcef bouchebaba said:

b) It  seems  that I can not load both code  (.txt) of cpu1 and cpu3  to flash  memory.  I can load only the code  of  cpu1 to the flash, however the code  of cpu3 it can be loaded only to the RAM  ?

That is correct as a future version of the flash plug in will support loading code with CPU3. 

In addition, for future questions that are on a different topic, please start a new thread, so we can keep all the toptics separate and threads don’t diverge from the original conversation. 

Best Regards,

Aishwarya

Youcef,

Checking in to see if the issue was resolved and/or you had any other questions.

Best Regards,

Aishwarya