Tool/software:
Hello TI Community,
I am working on implementing a three-phase interleaved LLC converter based on the SPRAD15 application report, which outlines a Type-4 PWM configuration for primary and secondary-side driving. According to the document, at least 6 PWM modules are required for the three-phase LLC topology (primary-side control). However, in my design using the TMS320F280039, I also need 4 additional high-resolution HRPWM channels for other critical functions. Given that the F280039 has only 8 PWM modules, I am exploring whether the Configurable Logic Block (CLB) can be utilized to generate the secondary-side driving signals without consuming dedicated PWM resources.
Key Questions:
- 1.
CLB Feasibility for Secondary-Side PWM Generation
The SPRAD15 document describes a primary-side control scheme using PWM modules. For the secondary-side synchronous rectification (SR) or driving logic, is it possible to replace PWM modules with CLB-generated signals? For example:- Can CLB’s finite state machines (FSMs), counters, and LUTs replicate the required PWM waveforms (e.g., phase-shifted signals, dead-time management)?
- Are there existing examples or reference designs where CLB has been used for similar LLC secondary-side control?
- 2.
Timing and Synchronization Challenges
- How to ensure precise synchronization between CLB-generated secondary-side signals and the primary-side PWM (e.g., avoiding shoot-through, maintaining interleaving phases)?
- Does the CLB’s 32-bit counter resolution suffice for high-frequency LLC applications (e.g., 200-500 kHz switching frequencies)?
- 3.
Resource Allocation Trade-offs
- What CLB resources (tiles, LUTs, FSMs) would be consumed for this implementation? For instance, does generating three-phase secondary signals require multiple CLB tiles, and would this impact other CLB-dependent functions (e.g., fault handling, custom logic)?
- 4.
Integration with Existing PWM Modules
- Can CLB outputs directly interface with GPIOs or other peripherals (e.g., eCAP, eQEP) to trigger secondary-side drivers?
- Are there limitations in signal propagation delays compared to dedicated PWM modules?
Context and Attempts:
- I reviewed the CLB Tool documentation and examples (e.g., motor control PTO, encoder decoding). While these demonstrate CLB’s flexibility, I’m unsure how to adapt them for LLC-specific requirements.
- The TI technical article on CLB 3 mentions its use in replacing external FPGAs/CPLDs for PWM protection and logic, which aligns with my goal. However, LLC secondary-side driving may demand stricter timing.
- In the HHC LLC design 2, CLB is used for SR control and primary PWM synchronization, suggesting partial applicability.
Request for Guidance:
- Are there CLB configuration templates or code snippets tailored for LLC secondary-side driving?
- What are the critical pitfalls to avoid when using CLB for high-frequency PWM-like signals?
Any insights or references would be greatly appreciated!
Best regards,
Jiang Jiahui
