This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28379D: LaunchXL TMS320F28379D & THS4521-HT

Part Number: TMS320F28379D
Other Parts Discussed in Thread: THS4521, , TINA-TI

Tool/software:

Here is a brief summary of my current work and the issue I’m encountering: ere is a brief summary of what I am doing:
  1. System Setup:
    I am working on a Phase-Shifted Full-Bridge (PSFB) isolated DC-DC converter. For sensing the output voltage and inductor current, I’m using a Fully Differential Op-Amp (TI THS4521 SHKJ). The sensed signals pass through an RC filter (500 Ohms & 2nF) placed at the differential output of the op-amp before being connected to the ADC pins of a DSP (LaunchXL TMS320F28379D) configured in differential mode. My operating frequency is 300 kHz.  
    • I trigger ePWM1 interrupt at TBPRD = 0 and use SOCA and SOCB at TBPRD/8 and TBPRD*5/8, respectively, to oversample and average the signal. I’d be happy to explain my reasoning behind this in more depth.
  2. Problem Description:
    The sensed signals are accurate only up to a certain voltage and current—approximately 120 V for voltage and 0.68 A for current.

    • Voltage sensing: Beyond 120 V, the sensed signal begins to increase very slowly and seems to saturate, despite the actual voltage rising further.

    • Current sensing: Similar behavior is observed after 0.68 A, though the signal remains accurate up to around 170 V output.

    I’ve already tried adding a buffer op-amp, but that didn’t help. Changing the RC filter’s cutoff frequency shifts the saturation point slightly but still gives the best results near 120–130 V. My goal is to sense up to 200 V reliably.

  3. Questions I Have:

    1. How does the RC filter at the ADC input affect the signal conditioning process, especially in differential mode sensing?

    2. Could this behavior be due to an impedance mismatch between the op-amp and ADC input? If so, how does that manifest in this case?

    3. What acquisition period (ACQPS) should I consider ideal? I’ve tested values from 80 to 250. Currently, I’m using ACQPS = 120, and I can explain why I use this value in more detail if needed.

    4. Is there anything in the interrupt generation process that you think I should look into further?

  • One of our team members will get back to you on this soon

  • Hello,

    1. How does the RC filter at the ADC input affect the signal conditioning process, especially in differential mode sensing?

      RC filter is mostly to help attenuate high-frequency noise before ADC sampling. However in differential mode, the RC filter needs to maintain balance on both positive and negative paths. Mismatch in resistance or capacitance between the two lines can reduced dynamic range or premature saturation.
    2. Could this behavior be due to an impedance mismatch between the op-amp and ADC input? If so, how does that manifest in this case?

      Yes, THS4521 output impedance is expected a sufficiently low source impedance to charge its sampling capacitor within the defined ACQPS. The 500 Ω resistance might be borderline too high. you can refer to "ADC Input Circuit Evaluation for C2000 MCUs (TINA-TI) Application Report" for more information.
    3. What acquisition period (ACQPS) should I consider ideal? I’ve tested values from 80 to 250. Currently, I’m using ACQPS = 120, and I can explain why I use this value in more detail if needed.

      Conidering the RC filter you choose, I would increase  to ACQPS ~500. In general, you can refer to DS to find the minimum ACQPS as: 
    4. Is there anything in the interrupt generation process that you think I should look into further?

      You can try disabling averaging and sampling only one point in time to isolate whether the issue is in acquisition or processing.

    Best Regards,

    Masoud

  • Thanks Masoud for replying.
    I'll go through the "ADC Input Circuit Evaluation for C2000 MCUs (TINA-TI) Application Report".
    Furthermore, I think ACQPS of 120 should be good, as the ACQPS = 120 means the acquisition period is 605 ns {Acquisition time =  (ACQPS+1)* 5 ns}.

    I would reply soon after checking the hardware with the changes as suggested by you.

  • Dear Masoud,

    I have implemented the ADC filter as described in the application report you mentioned. Here are my observations:

    1. With the proper filter configuration and ACQPS = 160 (i.e., Tacq = 805 ns, switching frequency = 300 kHz), I am able to sense both current and voltage signals accurately over the full range.
    2. However, when I adjust the phase shift ratio (PHR) between 0.35 and 0.47, the sensed signals become inaccurate. Interestingly, when I further reduce the PHR to 0.3 or below, the sensing starts working correctly again.

    For reference, the phase shift ratio (PHR) is defined such that:

    •    -- PHR = 0.5 → 180° phase shift → maximum output voltage
    • PHR = 0 → 0° phase shift → zero output voltage

    Could you please help me understand what might be causing the sensing issue in the mid-range phase shift values? Also, any suggestions on how to make the sensing reliable across the entire PHR range would be highly appreciated.

  • You're dealing with a sensing accuracy problem at certain ranges of the phase shift ratio (PHR). This might indicate that your ADC sampling is occurring during an unstable part of the waveform. I recommend plotting the PWM and ADC SoC on the scope and tuning the ADC trigger to fit your application.