TMS320F28P659DH-Q1: CLA Data read

Hi Kita,

See section 4.6 to understand the data types.

https://software-dl.ti.com/C2000/docs/cla_software_dev_guide/faq.html?highlight=bus#how-is-data-shared-between-the-cla-and-c28x 

Please take a look at the CLA workshop training to understand how the buses are configured.

https://www.ti.com/video/5432122168001

I would also advise taking a look at the device datasheet it include a device block diagram. See section 7.9.2 Control Law Accelerator (CLA)

https://www.ti.com/lit/gpn/tms320f28p650dk 

Regards,

Ozino

Hi Ozino, 

It’s still not clear about this question. What I asked is not shown in the video/documents, please help to confirm the questions.

Best Regards

Kita

Kita Li said:

1. My customer would like to confirm that when the CLA is writing 32-bit data to share RAM, only the first 16-bit write was completed and then 16 bits were not written. At this point CPU1 is going to read the CLA data, will it read only the updated first 16-bit data? Or wait for the CLA to completely update this 32-bit data before CPU1 reads?

It is possible for the CPU1 to read before the CLA has completed a write. To avoid this case a handshake (interrupt, flag, etc) between the two processors can be used to indicate data write is complete and ready to be read by the CPU.

Kita Li said:

2. In TRM it's showed that CLA bus can perform 16 or 32-bit read/write. 16 or 32-bit read/write means that if access 16bit data, then will use 16bit data bus. If access 32bit data, then will use 32bit data bus. Does it has2 buses or 1 bus which is compatible A and B?

There is one bus capable of writing 16-bit and 32-bit data.