TMS320F280039C: Confirmation of Register Delay Timing During PLL Initialization

Chen-Chih Liu

Part Number: TMS320F280039C
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Dear Experts,

I noticed that the TRM specifies a requirement: after writing to the SYSPLLMULT register, a delay of 45 cycles is necessary. Without this delay, subsequent register writes may be lost.

However, in the function SysCtl_setClock(), I observed that there is no delay invoked after writing SYSPLLMULT; instead, SYSPLLCTL1 is written to immediately afterward. Could this sequence pose any potential risks? Is it still safe to use this implementation in C2000Ware?

For reference, I am using version C2000Ware_5_04_00_00.

Thanks and Regards,
CC

10 months ago

0 Stevan Duraskovic 10 months ago

TI__Expert 5670 points

Hello Chen,

That's a good catch. I will take a look at SysCtl_setClock() and see if that delay was taken into consideration. Could you let me know which C2000Ware example you are looking at though?

0 Chen-Chih Liu 10 months ago in reply to Stevan Duraskovic

Intellectual 340 points

Hello Stevan,

I used "..\C2000Ware_5_04_00_00\driverlib\f28003x\examples\flash\flashapi_ex1_programming" for my reference.

0 Stevan Duraskovic 10 months ago in reply to Chen-Chih Liu

TI__Expert 5670 points

Okay, I will update you soon.

+1 Prarthan Bhatt 10 months ago

TI__Genius 15676 points

Hi,

Any CPU writes to these registers requires a delay between subsequent writes to the same register otherwise a second write can be lost. Since SYSPLLMULT and SYSPLLCTL1 are different registers it doesnot require delay. Back-to-back write to same register under the restriction needs delay

Thanks

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TMS320F280039C: Confirmation of Register Delay Timing During PLL Initialization