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TMS320F28388D: PWM peripheral still enabled after performing XRSn reset while CPU is halted by debugger

Youssef Afifi
Prodigy 10 points
Part Number: TMS320F28388D


Tool/software:

After halting the ECU using a TRACE32 debugger ('break" command) followed by triggering an external XRSn reset the following was observed:

  1. System clock configurations are reset to default values
  2. PWM module is still enabled. PWM signal can be detected on output pins with a changed frequency corresponding to the reset clock configurations
  3. CPU appears to be still halted.

Is there an explanation why the PWM registers do not reset to their default values after an XRSn reset while the CPU is halted? Also is it possible for the CPU to remain halted by the debugger after an XRSn reset?

  • 0
    TI__Expert 4180 points

    Youssef,

    The ePWM modules have their own internal timers, counters, and logic blocks that allow them to generate PWM signals independently of the CPU. The ePWM modules can continue operating even after the CPU is halted, allowing for precise timing and waveform generation even in the absence of CPU control. This capability is achieved through independent hardware components within the ePWM module, allowing for various functionalities like triggering ADC conversions or generating synchronization signals. In essence, the ePWM module acts as a standalone, hardware-driven PWM generator, providing a robust and reliable mechanism for precise timing and waveform generation, even when the CPU is not actively processing data.

    Also, could you please check in your ePWM setup whether ePWM emulation mode is as following and NOT in FREE RUN

    Please refer the following video especially last portion to see how to halt CPU in debug window.

    Let us know if any questions.

    Regards,

    Sumit