Part Number: TMS320F280025
Other Parts Discussed in Thread: SYSCONFIG, C2000WARE
Tool/software:
Hello, expert:
When I was using the MotorControl_SDK, I found a problem related to the configuration of the CMPSS module:
We routed both CMPSS1 and CMPSS3 to TRIP7 via ePWM x-bar, and routed TRIP7 to DCAH and DCBH through the DC sub-module of ePWM, as shown in the following code:
EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle[cnt],
MTR1_DCTRIPIN, EPWM_DC_TYPE_DCAH);
EPWM_enableDigitalCompareTripCombinationInput(obj->pwmHandle[cnt],
MTR1_DCTRIPIN, EPWM_DC_TYPE_DCBH);
Based on the previous relevant configurations of CMPSS1 and CMPSS3, it can be known that if there is an overcurrent situation in the U/V/W three-phase (where the U phase only detects positive overcurrent, the W phase only detects negative overcurrent, and the V phase detects both positive and negative bidirectional overcurrent), then the outputs of CMPSS1 and CMPSS3, CTRIPH and CTRIPL, will both output high levels. This means that both DCAH and DCBH will obtain a high level. (Question 1: Is this point correct?)
Then, the next step is to configure the event of ePWMxA at this time, that is, when DCAH shows a high level, trigger DCAEVT1 (as shown in the following figure).
The code at this time is:
EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle[cnt],
EPWM_TZ_DC_OUTPUT_A1,
EPWM_TZ_EVENT_DCXH_HIGH);
In this way, the macro definition EPWM_TZ_EVENT_DCXH_HIGH means that when DCAH is at a high level, DCAEVT1 is triggered, thereby generating a protection signal. (Question 2: Is this point correct?)
However, the problem lies in the configuration of ePWMxB, as we have previously routed TRIP7 to DCBH. According to the same logic, when DCBH is at a high level, should DCBEVT1 be triggered (as shown in the following figure)?

However, the code at this time is indeed represented as:
EPWM_setTripZoneDigitalCompareEventCondition(obj->pwmHandle[cnt],
EPWM_TZ_DC_OUTPUT_B1,
EPWM_TZ_EVENT_DCXL_HIGH);
The macro definition EPWM_TZ_EVENT_DCXL_HIGH seems to imply that when DCHL is at a high level, the DCBEVT1 event is generated. Unfortunately, we didn't route TRIP7 to DCHL.
Question 3: Where does the problem occur here? Is the macro definition EPWM_TZ_EVENT_DCXL_HIGH used wrongly in the routine?
In addition:
I checked the sysconfig version of the F280025 routine and found the same configuration, as shown in the following figure:

If configured according to the sysconfig version, Digital Compare B Low is routed to TRIP1, and TRIP1 is the same as TZ1. TZ1 is routed to INPUTXBAR1, which is the nFAULT pin.
However, the nFAULT pin is valid at a low level, which means it is at a high level under normal circumstances. Therefore, according to the configuration in sysconfig, DCBL will always be at a high level. Is this reasonable?


