TMS320F28P650DK: EQEP example for low speed

Wayne Huang

Genius 16675 points

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

Tool/software:

Hi champs,

I am asking this for our customer.

In F28P65x TRM,

23.6 eQEP Edge Capture Unit

it has some descriptions to deal with low speed.

1. Do we have examples?

2. If speed range is broad, including high speed and low speed, do we have any example to show how to deal with it by EQEP?

C:\ti\c2000\C2000Ware_5_04_00_00\driverlib\f28p65x\examples\c28x\eqep

Is Ex2 a good example?

We are not sure if it is proper to answer the above two questions?

7 months ago

0 Wayne Huang 7 months ago

TI__Genius 16675 points

Hi champs,

1. For example, can it be used for low speed like 0.001 pps (pulse per sec)?

200MHz (SYSCLK) / 128 (CCPS = 7 max) / 2^16 (16-bit QCTMR) = 23.8 Hz

It seems QCTMR is not long enough for 0.001 pps...?

Is my understanding correct?

2. If 0.001 pps cannot be met, is there any other HW method to meet it?

0 Fleenor 7 months ago in reply to Wayne Huang

TI__Mastermind 24593 points

Hey Wayne,

Thanks for providing the details here. I will need a little more time to follow up with precise details.

I wanted to verify some things based on the information you provided above.

You are referring to the 16-bit QCTMR value highlighted in the diagram below?

I want to determine if there is a way to provide a divided down version of SYSCLKOUT (without affecting other modules operating on the same clock, something much less then 200MHz to enable this lower speed use-case.

Best Regards,

Zackary Fleenor

0 Wayne Huang 7 months ago in reply to Fleenor

TI__Genius 16675 points

Hi Zack,

Yes, I referred to 16-bit QCTMR you showed above.

Please keep me posted and see if there is a solution.

+1 Fleenor 7 months ago in reply to Wayne Huang

TI__Mastermind 24593 points

Hey Wayne,

The only way to generate a slower Peripheral Clock (PERx_SYSCLK) (resulting in a slower count rate) is to reduce the speed of either CPU1_SYSCLK or CPU2_SYSCLK to the desired frequency. This will produce a performance hit on the given core, but more importantly, the PERx_SYSCLK is used as the source for all of the following IPs: ADC, CMPSS, DAC, EPWM, ECAP, EQEP, I2C, AES, SDFM, FSI, PMBUS, BGCRC, SPI, SCI, EPG, CAN, UART, LIN, and MCAN.

Suppose the user adjusts PERx_SYSCLK to account for EQEP. In that case, they must also recognize the effect on any other peripherals they use in their application and ensure the timing deltas are accounted for. Any divider values are properly updated to maintain a proper IP-level functional frequency.

TI provides the SysConfig Clock Tree tool to simplify this effort. An example can be found by selecting the sidebar option shown in the screenshot at the link below.

https://dev.ti.com/sysconfig/#/config/?args=--product%20%2Fmnt%2Ftirex-content%2FC2000Ware_5_04_00_00%2F.metadata%2Fsdk.json%20--board%20%2Fboards%2FLAUNCHXL_F28P65X%20--device%20TMS320F28P650SK%20--package%20169NMR%20--variant%20TMS320F28P650SK6%20--context%20CPU1

Best Regards,

Zackary Fleenor

0 Wayne Huang 7 months ago in reply to Fleenor

TI__Genius 16675 points

Hi Zack,

Understand. Lowering SYSCLK is not proper in the application, but at least we understand that's the only way.

Thank you anyway.

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TMS320F28P650DK: EQEP example for low speed