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TMS320F28P650DK: Synchronization between CLA and CPU

Thao Truong
Prodigy 81 points
Part Number: TMS320F28P650DK


Tool/software:

Hello e2e team,

We are using the F28P65 with the CLA (Control Law Accelerator) and would like to learn more about synchronization between tasks running on the CLA and the CPU.

My questions are:

  1. How can we best implement synchronization between tasks on the CLA and the CPU?
  2. Are there specific methods or best practices that could help us achieve efficient timing coordination?

If anyone has experience in this area or can share examples of synchronization between the CLA and CPU, we would greatly appreciate your input.

Thank you in advance.

Best regards,

Thao Truong

  • 0
    Prodigy 81 points

    Hello everyone,

    I wanted to follow up on my previous post regarding the synchronization between tasks running on the CLA and the CPU on the F28P65. I have not received a response yet, and I’m still looking for insights on how to manage this interaction effectively. If anyone has experience or knowledge on this topic, I would greatly appreciate your input.

    Thank you.

    Best regards,
    Thao Truong

  • 0 in reply to Thao Truong
    TI__Mastermind 21420 points

    Hi Thao,

    I apologize for my delayed response. Both the CLA and CPU run off the device's SYSCLK, so there should be no worry about time domains in general. The below are some features that can be utilized for synchronization between the two cores:

    1. Software triggers of CLA tasks from the main CPU
      1. This can be done inside a CPU ISR if some CPU code needs to run directly before CLA task code. Usually in this case the ISR on the CPU is triggered by a peripheral directly but the CLA task for that condition is triggered by software.
    2. CPU end of task interrupt
      1. This allows the CPU code to run after a specific CLA task has finished executing. In this case the CLA task would be triggered directly from a peripheral and run its code, then when the task has finished the CPU ISR can run its code.  
    3. CLA/CPU message RAMs
      1. Variables in the message RAMs can be used for synchronization, for example the CLA would set a flag in the CLA-to-CPU message RAM once it has finished executing a specific line of code, indicating that the CPU can access some shared memory etc. 

    As you can see, the synchronization techniques would be application specific to the desired timing of the task and ISR execution and nature of the shared memory. Let me know if you have any specific questions about what to do for your application. Please upvote this response if it is helpful to you as well Slight smile

    Best Regards,

    Delaney