Tool/software:
Is it critical for CPU when VREFHIx is stabilized on 3.3V level after VDD 1.2V is already applied, but still before XRSn is released?
CH1 - VDDIO (yellow)
CH2 - VDD (green)
CH3 - VREFHIx (blue)
CH4 - XRSn (purple)
(Here VDDIO and VREFHIx have initial values 0.6V and 1.3V because VREFHIx ref. IC is powered from ext. 5V which appears earlier then 3V3 for VDDIO. But this only for test setup. In real device 5V and 3V3 will appear simultaneously.)
Thank you!
BR
Anton
