TMS320F280025: Spurious interrupts after HWBIST test

Andrea,

I believe I have the answer, there is an assumption in the stl_hwbist_s.asm file that the user is clearing the TIF(Timer Interrupt Flag) bit 15 inside the timer ISR.  However, clearing the TIF bit is not absolutely necessary for repeated timer ISRs, so I would need you to check to see if this is being done in your Timer 2 ISR. 

If TIF is not cleared, then you will get a Timer 2 INT on every HWBIST run(which is what you are seeing).Potentially this could happen even if you are clearing the bit, but that would assume the timer 2 period is ~same as the time between your micro runs, and I don't think this is the case.

Here's the background:

Before we enable interrupt logging before the HWBIST micro-run we save off the state of the timer1 and timer2 TCR regs(which contain the TIF and the TIE(Timer Interrupt Enable), before clearing the TIE bit to avoid spurious ISRs as we noted above

        MOVW    DP, #TmrRegs
        MOV     AL, @TMR1TCR            ; Save TCR registers in the ACC
        MOV     AH, @TMR2TCR

        AND     @TMR1TCR, #~(3 << 14)   ; Clear TIE bit without clearing TIF
        AND     @TMR2TCR, #~(3 << 14)   ; Clear TIE bit without clearing TIF

        EALLOW

        MOVW    DP, #HWBRegs
        MOVW    @CSTCGCR3, #0x0A        ; Start logging interrupts

Now, when we come back to context restore from the micro run we re-look at the stored versions of the TCR regs in the following code.

   ; Restore the CPU Timer 1 & 2 interrupt enable status. If the TCR.TIF bit
    ; is set and interrupts were enabled force the corresponding bit in IFR.
    ;
        MOVW    DP, #TmrRegs

        TBIT    AL, #14             ; Branch if TIE wasn't set
        SB      noEnableTIE1, NTC

        TBIT    @TMR1TCR, #15       ; Branch if TIE was set, but TIF isn't
        SB      enableTIE1, NTC
        OR      IFR, #(1 << 12)     ; Set the IFR flag for INT13

enableTIE1:
        MOV     AL, @TMR1TCR        ; Reenable CPU Timer 1 interrupts
        AND     AL, #~(1 << 15)     ; TIF is W1C, so take care not to clear it
        OR      AL, #(1 << 14)
        MOV     @TMR1TCR, AL

noEnableTIE1:
        TBIT    AH, #14             ; Check if TIE was set
        SB      noEnableTIE2, NTC

        TBIT    @TMR2TCR, #15       ; Branch if TIE was set, but TIF isn't
        SB      enableTIE2, NTC
        OR      IFR, #(1 << 13)     ; Set the IFR flag for INT14

enableTIE2:
        MOV     AL, @TMR2TCR        ; Reenable CPU Timer 2 interrupts
        AND     AL, #~(1 << 15)     ; TIF is W1C, so take care not to clear it
        OR      AL, #(1 << 14)
        MOV     @TMR2TCR, AL

noEnableTIE2:

If the TIE bit wasn't set(meaning the user was not using the Timer Interrupt) we skip to the next timer since we don't care about the TIF(and based on how the timers work, these are enabled from reset, so even if not used TIF will be set).

In your case, since Timer 1 isn't used we skip it and move on to Timer 2.

Now, since Timer 2 had TIE set, we fall through and then proceed to evaluate bit 15, TIF.  If it was set before we started the HWBIST, the assumption is that we caught it before the ISR was serviced, so it needs to be serviced when we return.

If the user is not intentionally clearing the TIF in the Timer 2 ISR, then this bit will always be set; and as such the ASM code will manually set the IFR bit corresponding to the Timer 2.

So, we have two options:

1)Clear the TIF bit in the Timer 2 ISR.  I think this is the simplest

2)Change the code stl_hwbist_s.asm to intentionally clear the TIF bit as part of the context save.  The worst this does it delay the timer 2 ISR by one timer 2 period.  The drawback here is that we have to re-compile the stl_diagnostic.lib, since the ASM file is part of that library.  The project does exist in C2000Ware, so its not too difficult, but an extra step depending on how you want to proceed.

Best,
Matthew