Tool/software:
#ifdef UNIPOLAR_MODULATION EALLOW;
/* ---------------------- EPWM 1 -------------------- */ /* Set timer period, period = CPUClockFreq/PWMfrequency*/
EPwm1Regs.TBPRD = period>>1;
/* Symmetric wave*/
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
/* Disable phase loading*/
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
/* Clock ratio to SYSCLKOUT*/
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;
/* SYSCLKOUT / 1*/
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
/* Sync with Sync in signal*/
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
/* Shadow load for PRD*/
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
/* Setup shadowing*/
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
/* Set Actions*/
EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
/* Set Dead Band, Rising Delay on 1A & Falling Delay on 1B*/
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
/* Active Low complementary mode (EPWMxB is inverted)*/
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
/* 1B is the source for Rising and Falling edge delay */
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
/* Delay at Rising and falling edge*/
EPwm1Regs.DBRED = deadband_rising;
EPwm1Regs.DBFED = deadband_falling;
/* ---------------------- End EPWM 1 ---------------------*/
/* ---------------------- EPWM 2 -------------------------*/
/* Set timer period, period = CPUClockFreq/PWMfrequency */
EPwm2Regs.TBPRD = period>>1;
/* Symmetric wave*/
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
/* Clock ratio to SYSCLKOUT*/
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;
/* SYSCLKOUT / */
EPwm2Regs.TBCTL.bit.CLKDIV = 0;
/* Enable phase loading*/
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
/* Sync with Sync in signal and pass through*/
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
/* Shadow load for PRD*/
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
/* Configure time base to count up when it receives the sync event */
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
/* Value fo 2 is for logic delay */
EPwm2Regs.TBPHS.half.TBPHS = 2;
/* Setup shadowing*/
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
/* Set Actions */
EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
EPwm2Regs.AQCTLA.bit.ZRO = AQ_NO_ACTION;
/* Set Dead Band for PWM1, Rising Delay on 1A & Falling Delay on 1B*/
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
/* Active high complementary mode (EPWMxA is inverted)*/
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
/* 1A for Rising& Falling*/
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
/* Delay at Rising and falling edge*/
EPwm2Regs.DBRED = deadband_rising;
EPwm2Regs.DBFED = deadband_falling;
/* ------------------ End Init EPWM n+1 ------------------ */
/* Clear TB counter*/
EPwm1Regs.TBCTR = 0x0;
EPwm2Regs.TBCTR = 0x0;
/* ADC SOC on A group at counter=zero */
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO ;
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST;
/* 为所有 PWM 模块发出同步信号*/
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
/* CPU 暂停跳闸的逐周期中断 */
EPwm1Regs.TZSEL.bit.CBC6=0x1;
EPwm2Regs.TZSEL.bit.CBC6=0x1;
/* 我们希望 OST/CBC 事件做什么 */
/* EPWMxA & B 将走低 */
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO;
EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO;
/* 软件强制跳闸以禁用逆变器 */
EPwm1Regs.TZFRC.bit.OST=0x1;
EPwm2Regs.TZFRC.bit.OST=0x1;
伊迪斯;
#endif
#ifdef UNIPOLAR_MODULATION
duty=_IQ24mpy（InvSine，InvModIndex）;
half_period=（（int32）EPwm1Regs.TBPRD）>>1;
/* _IQ24mpy（I8Q24（占空比）， I32Q0（half_period）） = I32 */
EPwm1Regs.CMPA.half.CMPA= _IQ24mpy（half_period，_IQ24mpy（duty，_IQ24（-1.0））））+half_period;
EPwm2Regs.CMPA.half.CMPA=_IQ24mpy（half_period，duty）+half_period;
#endif
这是单极调制的代码。我想知道 InvSine 和 InvModIndex 是如何配置的？
