Tool/software:
Hello,
I have been working on the TMS320F28386D device and have some question I could not find in the different documents available to the public.
- The TRM details that the MSGRAM X to Y and Y to X are two different memories. Are those memories two different memory blocks that can be accessed in parallel without interference?
- For all SRAMs and memory, do they contain ROW buffers or any other optimization mechanism capable of generating multicore interference?
- Interference will be generated in BUS-MATRIX2. Arbitration rules state that CM has higher priority over other masters (uDMA and EthDMA). However, arbitration between uDMA and EthDMA is not stated.
- What is the CM_RAM_TESTERROR_LOG is (interrupt)?
- Can we state for sure that reserved interrupts will not trigger during the system's execution?
- No reference to CIPC is made in the currently known documentation, this is an interrupt (see Table 3-4 of TRM) but we do not know where it comes from. Do you have more information on that?
- The TRM is not clear regarding SDFM interrupt. It states in the SDFM section (28.1) that only SDy_ERR and SDyFTLx_DRINT are present but the interrupt list for CLA / CPUs do not show the same.
- I2CA seems to have two interrupts lines INT1.9 and INT8.1. Should it be I2CA and I2CB?
- The MPOST interrupt is not defined, it seems that only CPU1 is connected to MPOST features. What is it exactly?
- CANA_IFx are repeated in Table 11-1. Should it read CANB?
Thanks,
Alexy
