TMS320F28379D: EPWM configuration and epwm isr interrupt

Hello,

To configure 3 EPWM modules (1, 2, 3) on CPU1 and 3 EPWM modules (4, 5, 6) on CPU2, with epwm4 triggering an ISR interrupt on CPU2, the following configurations are required:

CPU1:

• Configure EPWM modules 1, 2, and 3 using the EPWM registers (e.g., EPWM1CTL, EPWM2CTL, EPWM3CTL, etc.).
• Set the EPWM module clock source, mode, and other parameters as needed.
• Ensure that the EPWM modules are enabled and running.

CPU2:

• Configure EPWM modules 4, 5, and 6 using the EPWM registers (e.g., EPWM4CTL, EPWM5CTL, EPWM6CTL, etc.).
• Set the EPWM module clock source, mode, and other parameters as needed.
• Ensure that the EPWM modules are enabled and running.
• Configure the interrupt system to enable the EPWM4 ISR interrupt on CPU2. This typically involves:
  • Setting the interrupt enable bit for EPWM4 in the PIE (Peripheral Interrupt Enable) register.
  • Setting the interrupt priority and vector address for EPWM4 in the PIE and PIEm (Peripheral Interrupt Enable Module) registers.
  • Writing the ISR (Interrupt Service Routine) code for EPWM4 and enabling it.

If all ePWM module configurations are set up on CPU1, but the epwm4 ISR interrupt needs to be enabled on CPU2, the following configurations are required:

CPU1:

• Configure all 6 EPWM modules (1, 2, 3, 4, 5, 6) using the EPWM registers.
• Set the EPWM module clock source, mode, and other parameters as needed.
• Ensure that the EPWM modules are enabled and running.

CPU2:

• Configure the interrupt system to enable the EPWM4 ISR interrupt on CPU2. This typically involves:
  • Setting the interrupt enable bit for EPWM4 in the PIE (Peripheral Interrupt Enable) register.
  • Setting the interrupt priority and vector address for EPWM4 in the PIE and PIEm (Peripheral Interrupt Enable Module) registers.
  • Writing the ISR (Interrupt Service Routine) code for EPWM4 and enabling it.
• Note that CPU2 does not need to configure the EPWM module itself, as it is already configured on CPU1. However, CPU2 needs to enable the interrupt for EPWM4 to handle the interrupt.

 Hope this helps.

Thanks for the response.

Actually in second case in which all configuration is in cpu1 and isr in cpu2, I had to enable isr configurations in both CPU's then only isr interrupt works in cpu2.

It didn't work as the configuration told by you. So am I missing something other than these configurations?  

Hello Akash,

You are correct that in the second case, where all EPWM module configurations are set up on CPU1 and the EPWM4 ISR interrupt needs to be enabled on CPU2, you need to enable the ISR configurations on both CPUs.

The reason for this is that the interrupt enable bit for EPWM4 needs to be set on both CPUs because the interrupt enable bit is a per-CPU setting, and each CPU needs to be aware of the interrupt enable status.

In addition to setting the interrupt enable bit on both CPUs, you also need to ensure that the interrupt priority and vector address are set correctly on CPU2, as I mentioned earlier.