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TMS320F28335-Q1: Queries Regarding SPI

TI-CSC
Genius 12945 points
Part Number: TMS320F28335-Q1

Tool/software:

Hello E2E Experts,

Good day.

We are using P/N: TMS320F28335ZJZQ in our data acquisition project, I have two queries mentioned below 

1) In Technical Reference Manual, it mentioned that if 'TALK' Bit of SPICTL Register is disabled transmission data, Default state of SIMO pin will be in high impedance

But If TALK' Bit of SPICTL Register is enabled, then no transmission data is written to SPITXBUF Register & there is no previous transmission data in SPITXBUF Register, What will be default state of SIMO pin? clearly 

2) I have same above query in McBSP-A&B configured as SPI. What is the default state of SIMO pin is enabled for transmission if there is no transmission data written & no previous transmission data? 

I appreciate a clear explanations.

Regards,

TICSC

  • 0
    TI__Genius 10876 points

    Hello,

    1. Per Figure 9-5. SPICLK Signal Options in the device TRM, the expected idle state of the SPISIMO/SPISOMI is the prev. data bit. If there is no prev. data, then the state of the pin should be based on the presence of internal or external pull-up/pull-downs. If there are no external pull-up/pull-downs and the internal ones are unused, then the state is, I believe, not explicitly defined. 
    2. The above should apply to McBSP as well.

    Regards,
    Jason Osborn

  • 0 in reply to Jason Osborn
    TI__Genius 12945 points

    Hello Jason,

    Good day.

    When CS is low; Transmit is enabled; no transmission data; no previous data; no internal/external pullup & pulldown, I need clear information what will the default state of "SIMO" from below of these states:
    a) Low state
    b) High State
    c) High Impedance
    d) Don't Care
    Tell me very clearly what will be default "SIMO" from above mentioned states?

    Regards,

    TICSC

  • 0 in reply to TI-CSC
    TI__Genius 10876 points

    If there is no action being done whatsoever on the pin, then the state of the pin is not defined, based on my understanding. This most closely corresponds to (D) from the options you provided.

    The most likely state of the pin is, I believe, (A), based on typical GPIO configurations and common convention, but that is not guaranteed by anything.

    Regards,
    Jason Osborn