TMS320F28386D: TMS320F28386D SRAM design and capabilities

Alexy Torres

Part Number: TMS320F28386D

Tool/software:

Hello,

I am currently working on the TMS320F28386D would need to know the inner mechanism of the SRAMs to determine their potential interference in a multicore environment.
For all SRAMs and memories, do they contain ROW buffers or any other optimization mechanism capable of generating multicore interference?

Thanks,
Alexy

3 months ago

0 Vivek Singh 3 months ago

TI__Guru** 115271 points

I am not clear on this query. These are single port memory blocks and accesses from multiple initiators are arbitrated using round robin scheme to provide single access at any time.

Vivek Singh

0 Alexy Torres 3 months ago in reply to Vivek Singh

Prodigy 60 points

Thanks, I understand the access scheme but I was wondering if there were any caches/buffers inside the SRAM or if accesses are directly made to the memory block (that itself does not contain buffer or such)?

Alexy

+1 Vivek Singh 3 months ago in reply to Alexy Torres

TI__Guru** 115271 points

No caches. Accesses are made directly to memory.

Vivek Singh

0 Alexy Torres 3 months ago in reply to Vivek Singh

Prodigy 60 points

Thank you for the answer!

Alexy

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TMS320F28386D: TMS320F28386D SRAM design and capabilities