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TMS320F28386D: TMS320F28386D Interrupts clarifications and questions

Alexy Torres
Prodigy 60 points
Part Number: TMS320F28386D

Tool/software:

Hello,

While analyzing the TMS320F28386D design, I found multiple inconsistencies in the TRM about interrupts. Could you clarify the following information?

What are the CM_RAM_TESTERROR_LOG, CIPC, MPOST and SDFM interrupts?
The TRM states in the SDFM section (28.1) that only SDy_ERR and SDyFTLx_DRINT are present but the interrupt list for CLA / CPUs do not show the same.
It seems that only CPU1 is connected to MPOST features. What is it exactly?

I2CA seems to have two interrupts lines INT1.9 and INT8.1. Should it be I2CA and I2CB?
CANA_IFx are repeated in Table 11-1. Should it read CANB?


Thanks,
Alexy

  • 0
    TI__Mastermind 18345 points

    Hi Alexy,

    I apologize for my delayed response. Below are answers to your last three questions, I will get back to you with explanations for the first two questions soon.

    Alexy Torres said:

    It seems that only CPU1 is connected to MPOST features. What is it exactly?

    MPOST is the "Memory Power on Self-Test" module, see the description below. The application note linked here goes into some more detail as well. 

    Alexy Torres said:
    I2CA seems to have two interrupts lines INT1.9 and INT8.1. Should it be I2CA and I2CB?

    It looks like both of these interrupts do the same thing when configured but the INT1.9 can be used if the application requires I2C to have a high priority in the PIE, whereas the INT8.1 would be used if you want I2CA operations to have a lower priority. It basically just avoids the need to implement interrupt nesting in order to have a high priority I2C interrupt. I don't believe this is explicitly explained in the documentation anywhere so I will make sure a clarification is added.

    Alexy Torres said:

    CANA_IFx are repeated in Table 11-1. Should it read CANB?

    Yes, the bottom three should say CANB_IFx. I confirmed with the software enums below from the SDK:

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    Prodigy 60 points

    Hi Delaney,

    Thank you for the answers.
    Did you get any feedback for the rest of the questions?

    Best regards,
    Alexy

  • 0 in reply to Alexy Torres
    TI__Mastermind 18345 points

    Hi Alexy,

    Thank you for your patience. Below are the answers to the rest of your questions:

    Alexy Torres said:
    What are the CM_RAM_TESTERROR_LOG, CIPC, MPOST and SDFM interrupts?
    Alexy Torres said:
    The TRM states in the SDFM section (28.1) that only SDy_ERR and SDyFTLx_DRINT are present but the interrupt list for CLA / CPUs do not show the same

    The SDFM1 / SDFM2 interrupts in the PIE table are the SDy_ERR interrupts and the SDFMyDRx interrupts are the SDyFTLx_DRINT interrupts. I see how this is a little confusing because the names used in the PIE are different.

    Please upvote any responses that were helpful to you. Slight smile

    Best Regards,

    Delaney