Tool/software:
Dear expert,
Now I use the Fapi to build a BL and set the code in the bank0 and take it running in the RAM, erase / program the bank1, I program the Bank1 successfully as picture1, but when enter re-debug mode, the bank1 seems blank again by the Memory Browser(as picture2).
Could you give some advices about this? Thank you.
Hi Rajeshwary,
According to the document description, this part is running in RAM.
Hi Rajeshwary,
While receive the records from the GUI, the target(as slave) seems hold the SCL as the attachments show.
Meanwhile, I have check the register status, which indicate it’s not in the slave transmitter mode(I2CSTR .SDIR =0, I2CMDR.TRX=0)
At this case I’ll read the resister to the Rxbuf.
As the slave-receiver mode description it should not hold the SCL low, so what other factors might cause this situation? Thx
