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LAUNCHXL-F28P65X: Application Not Running After DCAN Flashing on F28P65x Using dcan_flash_programmer.exe with CAN Tool: PEAK CAN

Part Number: LAUNCHXL-F28P65X
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Hello TI Team,

I am currently working on DCAN flash programming for the F28P65x device,here i am using PEAK CAN, The goal is to flash and run an application on CPU1 using the CAN peripheral with the provided DCAN flash kernel and flash programmer utility.

Flashing Command:C:\ti\C2000Ware_5_04_00_00\utilities\flash_programmers\dcan_flash_programmer>dcan_flash_programmer.exe -d f28p65x -k dcan_flash_kernel_c28x_dual_ex5.txt -a

The application seems to load successfully, as shown in the following console output: led_ex1_c28x_dual_blinky_cpu1.txt -v

Steps:

1.Set the boot mode to CAN: S3 with GPIO72 high and GPIO84 low.

2.loaded the -d f28p65x -k dcan_flash_kernel_c28x_dual_ex5.txt -a led_ex1_c28x_dual_blinky_cpu1.txt -v

3.after application loaded the GPIO72 Low and GPIO84 High, then Reset the Boad , but my application was not running.

Any guidance, example projects, or best practices would be highly appreciated.

Note:After resetting the board, the application does not run. The expected blinking behavior from led_ex1_c28x_dual_blinky_cpu1 is not observed.

Thank you in advance for your support.

Best regards,

Suresh k

  • HI Suresh,

    The DCAN flash kernel programs your application to flash, so to run it after a reset you must boot from flash. To boot from flash, both GPIO72 and GPIO84 should be high. Setting 72 low and 84 high configures the device for SCI boot.

    Best,

    Alex

  • Hi Alex,

    I am trying to flash a "led_ex1_c28x_dual_blinky_cpu1" program via DCAN_programmer into my LaunchPad F28P65x. I have followed the steps given document of , but the program is not being flashed. I have followed the following steps:

    1. Setting the correct Boot Mode-S3 by setting GPIO72 (DOWN)-> 0 and GPIO84 (UP) ->1(after application is loaded then set up the S3 both pins to High)
    2. Setting S4 DOWN to XCVR(CAN Route).
    3. Connected HIGH and LOW pins of the transceiver at J14 of the LaunchPad to Channel 1 of PCAN-USB.
    4. Importing the "flash_kernel_ex5_dcan_flash_kernel.c" project and Build done
    5. Adding "${CG_TOOL_HEX}" "${BuildArtifactFileName}" -boot -sci8 -a -o "${BuildArtifactFileBaseName}.txt" to the "flash_kernel_ex5_dcan_flash_kernel.c" project.
    6. Enabling the C2000 Hex Utility and adding the flags: --diag_wrap=off --boot --sci8 --ascii in the "flash_kernel_ex5_dcan_flash_kernel.c" project.
    7. Copying the generated two txt files to the "dcan_flash_programmer" directory and running the command: dcan_flash_programmer.exe -d         f28P65x -k  dcan_flash_kernel.txt -a led_ex1_c28x_dual_blinky_cpu1 -v
    8. The cmd window shows "Kernel Loaded" and "Application Load Completed"--> please refer the image, but the led application not running on the board.
      

    10.Obeserved one more thing, if i removed the connection from PEAK CAN USB to J14(CAN-H/CAN-L)-onboard, then also it's showing "Application load completed " which means kernal and Application not loaded into the board.

    Note :i am using the PEAK CAN USB, is it possible to update the Firmware, using this dcan_flash_programmer {Flashing Command:C:\ti\C2000Ware_5_04_00_00\utilities\flash_programmers\dcan_flash_programmer>dcan_flash_programmer.exe -d f28p65x -k dcan_flash_kernel_c28x_dual_ex5.txt -a}?

    ->Modified Byte 3 and Byte 4 in the output (dcan_flash_kernel_c28x_dual_ex5 .txt) file as follows: AA 08 C0 7A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02

     Observations:

    -Console shows: **"Kernel Loaded"** and **"Application Load Completed"**
    - However, **application is not running** — LED doesn't blink
    - Even if I disconnect the PEAK CAN USB from the board, it **still shows the same messages**, suggesting it's not actually sending anything over CAN

    My Questions:

    1. Does `dcan_flash_programmer.exe` officially support PEAK CAN USB (PCAN-USB) adapters?
    2.  Is there any way to use PCAN-USB with this programmer or any workaround?
    3. If not, what CAN adapter does TI recommend using with this utility for F28P65x Launchpad?
    4. How can I confirm if the flash kernel was truly loaded into RAM, and the application written to Flash?

    Any suggestions would be greatly appreciated.

    Best Regards,

    Suresh k.

  • Part Number: LAUNCHXL-F28P65X

    Tool/software:

    Hello TI Team,

    I'm attempting to flash the led_ex1_c28x_dual_blinky_cpu1 application onto my F28P65x LaunchPad using the dcan_flash_programmer utility from C2000Ware (v5.04.00.00). I'm using a PEAK CAN USB device for the CAN interface.

    Here’s what I’ve tried so far:

    Boot Mode Configuration:

    GPIO72 = 0 (DOWN), GPIO84 = 1 (UP) for DCAN boot.

    S4 switch is set to route CAN through XCVR.

    Hardware Setup:

    Connected PEAK CAN USB Channel 1 (CAN-H and CAN-L) to J14 on LaunchPad.

    Kernel and Application Generation:

    Built dcan_flash_kernel_c28x_dual_ex5 from C2000Ware examples.

    Added post-build step:
    "${CG_TOOL_HEX}" "${BuildArtifactFileName}" -boot -sci8 -a -o "${BuildArtifactFileBaseName}.txt"

    Hex Utility flags: --diag_wrap=off --boot --sci8 --ascii

    Generated .txt for both kernel and application (blinky).

    Flashing Command:

    dcan_flash_programmer.exe -d f28p65x -k dcan_flash_kernel_c28x_dual_ex5.txt -a led_ex1_c28x_dual_blinky_cpu1.txt -v

    Output shows:

    “Kernel Loaded”

    “Application Load Completed”

    But blinky application does not run.

    Observation:

    Even when the CAN connection is physically removed, the programmer still prints “Application Load Completed,” which suggests the tool may not actually communicate with the target via PEAK CAN.

    Note:

    I manually edited Byte 3 and 4 in the kernel hex file to:
    AA 08 C0 7A ... based on older documentation.

     My Questions:

    1.Is PEAK CAN USB officially supported for use with dcan_flash_programmer.exe?

    2.If not, what CAN adapter should be used (TI’s recommended one)?

    3.How can I verify if the kernel is actually running and flashing the application?

    4.Is there a modified version of the DCAN programmer that supports PEAK CAN USB?

    5.Could the format or checksum of the .txt files be causing the issue?

    Any suggestions would be greatly appreciated.

    Best Regards,

    Suresh

  • Hi Suresh,

    1.Is PEAK CAN USB officially supported for use with dcan_flash_programmer.exe?

    - Yes

    2.If not, what CAN adapter should be used (TI’s recommended one)?

    - The PEAK USB adapter is recommended

    3.How can I verify if the kernel is actually running and flashing the application?

    - While the kernel is running, connect to the device, halt, and load the symbols for the kernel

    - After "Application load completed", you can connect to the device and inspect the contents of flash using the memory browser.

    - You can also use the on-chip flash tool in CCS to verify the contents of flash against your .txt/.out

    4.Is there a modified version of the DCAN programmer that supports PEAK CAN USB?

    - N/A

    5.Could the format or checksum of the .txt files be causing the issue?

    - Can you confirm that bytes 3 and 4 of the text file have been replaced with the hex value calculated from the final result of the bit timing register value (CAN_CALC_BTRREG) in order of least significant byte followed by the most significant byte?

    "${CG_TOOL_HEX}" "${BuildArtifactFileName}" -boot -sci8 -a -o "${BuildArtifactFileBaseName}.txt"

    Hex Utility flags: --diag_wrap=off --boot --sci8 --ascii

    When using the post-build step, you can disable the hex utility

    GPIO72 = 0 (DOWN), GPIO84 = 1 (UP) for DCAN boot.

    This is now selecting SCI boot? You had it right initially (72 = 1, 84 = 0) for CAN boot, the needed change for the application to boot after a power cycle was to switch to flash boot (72=1, 84=1) after running the kernel and writing the application to flash.

    Best,

    Alex

  • Hi Alex

    - Can you confirm that bytes 3 and 4 of the text file have been replaced with the hex value calculated from the final result of the bit timing register value (CAN_CALC_BTRREG) in order of least significant byte followed by the most significant byte?--> Yes i am using below Bit Timing

    #define CAN_CALC_BITRATE  1000000U
      #define CAN_CALC_CANCLK   20000000U
     #define CAN_CALC_BITTIME  20 
    Byte 3 (0xC0) and Byte 4 (7A)
    I have few more questions:
    Questions
    1.What value should be passed to uint16_t XTAL_frequency? )device.h) 
     #define USE_PLL_SRC_XTAL
     #define USE_PLL_SRC_INTOSC
    2. Application_Flash_Banks[5] = {0,1,2,3,4};-->is it possible to use single flash bank
    3. uint16_t switchToXTAL -->what is the parameter value need passe here 0 or 1?
    4.in linker .cmd file is it possible to modify"
    "could you pls refer the below code snipet and .cmd file formate":
    extern uint32_t DCAN_Boot(uint32_t bootMode, uint32_t bitTimingRegValue,
                              uint16_t switchToXTAL, uint16_t XTAL_frequency,
                              uint16_t numBanksToErase, uint32_t* flashBanksToErase,
                              uint32_t* WE_Protection_Mask_A,uint32_t* WE_Protection_Mask_B,
                              uint32_t* WE_Protection_OTP_Mask);

    //
    // main - This is an example code demonstrating F021 Flash API usage.
    //        This code is in RAM
    //
    uint32_t main(void)
    {

        //
        // Initialize device clock and peripherals
        Device_init();

        //
        // Call Flash Initialization to setup flash waitstates. This function must
        // reside in RAM.
        //
        Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES);

        //
        // Initialize GPIO
        //
        Device_initGPIO();
     
        //
        // Initialize DCAN and wait to receive messages
        //
        uint32_t Application_Flash_Banks[5] = {0,1,2,3,4};
        uint32_t WE_Protection_A_Masks[5] = {0,0,0,0,0};
        uint32_t WE_Protection_B_Masks[5] = {0,0,0,0,0};
        uint32_t WE_Protection_OTP_Masks[5] = {0,0,0,0,0};

     return DCAN_Boot(CAN_BOOT_ALT1_SENDTEST, 0, 1, 20, 5, Application_Flash_Banks,
                         WE_Protection_A_Masks, WE_Protection_B_Masks, WE_Protection_OTP_Masks);  
    MEMORY
    {
       /* BEGIN is used for the "boot to SARAM" bootloader mode   */
       BEGIN            : origin = 0x000000, length = 0x000002
       BOOT_RSVD        : origin = 0x000002, length = 0x0001AF     /* Part of M0, BOOT rom will use this for stack */
       RAMM0            : origin = 0x0001B1, length = 0x00024F
       RAMM1            : origin = 0x000400, length = 0x000400

       RAMD0            : origin = 0x00C000, length = 0x002000
       RAMD1            : origin = 0x00E000, length = 0x002000
       RAMD2            : origin = 0x01A000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
       RAMD3            : origin = 0x01C000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
       RAMD4            : origin = 0x01E000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
       RAMD5            : origin = 0x020000, length = 0x002000  // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection

       RAMLS0           : origin = 0x008000, length = 0x000800
       RAMLS1           : origin = 0x008800, length = 0x000800
       RAMLS2           : origin = 0x009000, length = 0x000800
       RAMLS3           : origin = 0x009800, length = 0x000800
       RAMLS4           : origin = 0x00A000, length = 0x000800
       RAMLS5           : origin = 0x00A800, length = 0x000800
       RAMLS6           : origin = 0x00B000, length = 0x000800
       RAMLS7           : origin = 0x00B800, length = 0x000800
       RAMLS8           : origin = 0x022000, length = 0x002000  // When configured as CLA program use the address 0x4000
       RAMLS9           : origin = 0x024000, length = 0x002000  // When configured as CLA program use the address 0x6000

       // RAMLS8_CLA    : origin = 0x004000, length = 0x002000  // Use only if configured as CLA program memory
       // RAMLS9_CLA    : origin = 0x006000, length = 0x002000  // Use only if configured as CLA program memory

       RAMGS0           : origin = 0x010000, length = 0x002000
       RAMGS1           : origin = 0x012000, length = 0x002000
       RAMGS2           : origin = 0x014000, length = 0x002000
       RAMGS3           : origin = 0x016000, length = 0x002000
       RAMGS4           : origin = 0x018000, length = 0x002000

       /* Flash Banks (128 sectors each) */
       FLASH_BANK0     : origin = 0x080000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
       FLASH_BANK1     : origin = 0x0A0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
       FLASH_BANK2     : origin = 0x0C0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
       FLASH_BANK3     : origin = 0x0E0000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
       FLASH_BANK4     : origin = 0x100000, length = 0x20000  // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection



       // CPU1TOCPU2RAM    : origin = 0x03A000, length = 0x000400
       // CPU2TOCPU1RAM    : origin = 0x03B000, length = 0x000400

       // CLATOCPURAM      : origin = 0x001480,   length = 0x000080
       // CPUTOCLARAM      : origin = 0x001500,   length = 0x000080
       // CLATODMARAM      : origin = 0x001680,   length = 0x000080
       // DMATOCLARAM      : origin = 0x001700,   length = 0x000080

       // CANA_MSG_RAM     : origin = 0x049000, length = 0x000800
       // CANB_MSG_RAM     : origin = 0x04B000, length = 0x000800
       RESET            : origin = 0x3FFFC0, length = 0x000002
    }


    SECTIONS
    {
       codestart        : > BEGIN
       .text            : >> RAMGS0 | RAMGS1 | RAMGS2
       .cinit           : > RAMM0
       .switch          : > RAMM0
       .reset           : > RESET, TYPE = DSECT /* not used, */

       .stack           : > RAMM1
    #if defined(__TI_EABI__)
       .bss             : > RAMLS8
       .bss:output      : > RAMLS8
       .init_array      : > RAMLS8
       .const           : > RAMLS8
       .data            : > RAMLS8
       .sysmem          : > RAMLS8
    #else
       .pinit           : > RAMLS8
       .ebss            : >> RAMLS8
       .econst          : > RAMLS8
       .esysmem         : > RAMLS8
    #endif

       Filter_RegsFile  : > RAMGS1

    #ifdef __TI_COMPILER_VERSION__
        #if __TI_COMPILER_VERSION__ >= 15009000
           .TI.ramfunc      : > RAMGS1
        #else
           ramfuncs         : > RAMGS1
        #endif
    #endif

       // MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
       // MSGRAM_CPU1_TO_CPU2_COPY_TO_M1_RAM > CPU1TOCPU2RAM, type=NOINIT
       // MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT

    }

    Any suggestions would be greatly appreciated.

    Best Regards,

    Suresh

  • 1.What value should be passed to uint16_t XTAL_frequency?

    - 20 and 25 will work, can you try using 25?

    2. Application_Flash_Banks[5] = {0,1,2,3,4};-->is it possible to use single flash bank?

    - These refer to the protection masks for each flash bank. See section 4.1.1 of CAN Flash Programming of C2000 Microcontrollers (Rev. A) for more information.

    3. uint16_t switchToXTAL -->what is the parameter value need passe here 0 or 1?

    - If using XTAL, it should be 0x1

    4.in linker .cmd file is it possible to modify?

    - Can you clarify this? The linker command file can be modified to place the kernel in a different region of memory.


    3.How can I verify if the kernel is actually running and flashing the application?

    - While the kernel is running, connect to the device, halt, and load the symbols for the kernel

    - After "Application load completed", you can connect to the device and inspect the contents of flash using the memory browser.

    - You can also use the on-chip flash tool in CCS to verify the contents of flash against your .txt/.out

    What was the result of this? Are you able to confirm that the application has been written to flash? Can you provide a screenshot or memory dump?

    Have you made any modifications to the kernel?

    Best,

    Alex

  • Hello Alex,

    I tried with this debugging but but, i m flashing via PEAK CAN USB.

    and i have few Questions:

    1. Boot Mode GPIO Switch (S3/S4 Configuration)
    I’m using the following boot mode pin configuration for DCAN:

    S3:
    GPIO72 = 1 (UP)

    GPIO84 = 1 (DOWN)

    This selects default DCAN boot mode (0x02), which uses GPIO58 (CANTX) and GPIO59 (CANRX).

    However, I want to switch to use boot mode 0x22, which uses GPIO4 (CANTX) and GPIO5 (CANRX) instead.

    Can you confirm what the S4 switch position needs to be to set BOOTDEF = 0x22?

    2. Changing BOOTDEF Value to 0x22
    If I want to use alternate CAN pins (GPIO4 and GPIO5) via boot mode 0x22, do I need to:

    Set the BOOTDEF value in OTP manually?

    -->Or is there a way to override it through software or other configuration?

    --> what’s the best practice for programming BOOTDEF = 0x22 into OTP to use alternate CAN pins?

    3. Flashing When OTP Is Programmed
    If the OTP already has a BOOTDEF value programmed, can I still update the firmware via can_flash_programmer.exe (using PEAK CAN USB)?

    Specifically, I'm using the following CAN configuration in my kernel:

    #define CAN_CALC_BITRATE 1000000UL // 1 Mbps
    #define CAN_CALC_CANCLK 20000000UL // 20 MHz
    #define CAN_CALC_BITTIME 20UL
    Is this configuration valid for 1 Mbps with 20 MHz CAN clock?

    4. Kernel Boot Code Snippet Validation
    Here's the code I'm using in the kernel to start DCAN boot with boot mode 0x22:

    EntryAddr = DCAN_Boot(0x22, 0, 0, 20, NUM_FLASH_BANKS, Application_Flash_Banks,
    WE_Protection_A_Masks, WE_Protection_B_Masks, WE_Protection_OTP_Masks);

    // Branch to application entry point
    asm(" MOVL XAR7, ACC ");
    asm(" LB *XAR7 ");
    5.Can you please confirm if the above code correctly initiates DCAN boot using BOOTDEF = 0x22?

    Do I need to call ExitBoot() or insert any delay before branching?

    #define CAN_CALC_BITRATE   1000000UL//1mbps
    #define CAN_CALC_CANCLK    20000000UL//20MHZ
    #define CAN_CALC_BITTIME   20UL
    6.can u pls look into this code snipet is it correct bcz i am using the 0x22
      EntryAddr = DCAN_Boot(0x22, 0, 0, 20, NUM_FLASH_BANKS, Application_Flash_Banks,
                         WE_Protection_A_Masks, WE_Protection_B_Masks, WE_Protection_OTP_Masks);

        // branch to application entrypoint
        asm(" MOVL  XAR7, ACC ");
        asm(" LB *XAR7 ");
        // ExitBoot();

        // while(1);  // Should not reach here.

        return (EntryAddr);    
    Best Regards,
    Suresh k
  • Hello,

    S3:
    GPIO72 = 1 (UP)

    GPIO84 = 1 (DOWN)

    Is GPIO84 1 or 0? This is unclear. CAN boot is 72=1, 84=0.

    Set the BOOTDEF value in OTP manually?

    Yes, you will have to program the correct BOOTDEF value using the Flash API. See Getting Started with Bootloading on C2000 Microcontrollers for more information. You can use emulation boot and EMU_BOOTDEF to test your configuration before writing to OTP.

    Best,

    Alex