TMS320F28388D: Does it support Hiperface DSL in CLB

Hi Jing,

Could you provide some basic block diagram or description of the HDSL functionality? I am not familiar with this protocol.

Note the CLB resources are very limited (only 3 counters, 3 FSMs, etc.), so it cannot achieve the same flexibility as a real FPGA.

Thank you,

Luke

Hi Luke,

I found this document from TI about an encoder interface design for C2000 MCU and AM437X: https://www.ti.com/lit/pdf/tiduan5

It has the figures for Hiperface DSL interface on page 8, hope it can explain the usage of this protocol:

This design support HDSL, but seems only for AM437x but not for C2000MCU. Could you confirm that with me?

Thanks,

Jing

Hi Jing,

In the product description it says TIDA-00179 is used, which uses either AM437x or F2837x. If F2837x support this I think F2838x should as well.

I am struggling to find a detailed digital circuit that represents the HDSL protocol. Would you be able to extract this from your FPGA design? I'm looking for a diagram that includes AND/OR/NOT gates, shift registers, etc. to show the exact behavior desired.

Thank you,

Luke

Hi Luke,

Unfortunately the FPGA design I used doesn't include the detailed logic for HDSL protocol. The HDSL protocol is represented by the IP core provided by SICK, and I only built the interface to the IP core in FPGA. 

Here I have another question, the Sitara AM437x seems support HDSL with PRU-ICSS, does it only provide the HDSL IP core interface or if it include the protocol logic as well?

Thanks,

Jing

Hi Jing, 

Thanks for your inquiry - since your latest post has a different device in question, please submit a new E2E on regarding that device so it can be routed to the correct team and expert. Thanks!

Best,

Allison

Hi, I will move my question regarding the AM437x to other forum, but I still would like to get the answer about F28388D:does it support the HDSL signal decoding? 

For example, as the TIDA-00179 encoder interface board claims it provides direct interface to the host processor like Delfino F28379, but I can't figure out how to interface the HDSL signal to the processor and how to process the HDSL encoder data. Any advice or reference documents?

Hi Jing,

Allison is currently out of office. Please expect a delay in response until next week when she returns. 

Best Regards,

Delaney