Other Parts Discussed in Thread: C2000WARE, TIDM-1007
Tool/software:
We are working in the implementation of the digital control for a 'bidirectional split-phase inverter.' So far we have have some success with VSI mode (inverter), but tunning the controllers in PFC mode is proving to be difficult.
So far we have base our control design following the TI 'TIDM_02008' design guide, but once we set heavier load at the Vbus
Topology: Bidirectional split-phase inverter (2-phase 3-leg).
System Description
We are working on the implementation of digital control for a bidirectional split-phase inverter. Our system is a 2-phase 3-leg topology (split-phase) that can operate in both Voltage Source Inverter (VSI) mode and Power Factor Correction (PFC) mode. So far, we have achieved reasonable success with VSI mode, but tuning the controllers in PFC mode is proving to be challenging.
Our control design is based on the TI TIDM_02008 design guide. While the system operates stably at low load levels, we encounter significant issues when attempting to increase the load current.
Issue Description
When the system is running in PFC mode with 220 Vac input and rectifying to 400 Vdc, the controller response exhibits unwanted oscillations that increase with load current. Specifically:
- The current waveform shows oscillation behavior rather than a clean sine wave
- The resonance frequency appears to be between 1 kHz and 1.3 kHz
- The oscillations become progressively worse as load current increases
- The system becomes unstable at approximately 2A, which is well below our target nominal current
We've observed that our PI controller settings (GI_PI_KP = 0.8000, GI_PI_KI = 0.0400) appear adequate for light loads but potentially too aggressive under higher current conditions.
The following are TI's original settings:
#define TTPLPFC_GI_PI_KP (float) 0.3496503407 #define TTPLPFC_GI_PI_KI (float) 0.0020000510 #define TTPLPFC_GV_PI_KP (float) 0.6004499882 #define TTPLPFC_GV_PI_KI (float) 0.0001000236 #define TTPLPFC_GI_PI_MAX ((float32_t)1.0) #define TTPLPFC_GI_PI_MIN ((float32_t)-1.0) #define TTPLPFC_GV_PI_MAX ((float32_t) 0.7) #define TTPLPFC_GV_PI_MIN ((float32_t)-0.02)
Attempted Solutions
We've experimented with:
- Various PI controller gain combinations
However, these adjustments have not resolved the core resonance issue.
Technical Implementation Details
- Implemented a two-phase PFC rectifier with a voltage-mode outer loop and current-mode inner loop
- SPLL parameters currently set to (222.2862, -222.034)
- Current controller operates at PWM switching frequency (50 kHz)
- Current processing in the PWM ISR.
- Voltage loop in a slower control ISR (10 kHz)
The following are TI's original settings:
SPLL_1PH_SOGI_config(&TTPLPFC_spll1,
TTPLPFC_AC_FREQ,
TTPLPFC_CONTROL_ISR_FREQUENCY,
(float32_t)(222.2862),
(float32_t)(-222.034));
We suspect the issue may involve:
- Possible coupling between voltage and current control loops
- SPLL sensitivity affecting stability under load conditions
Also, I'm not an expert in digital control implementation so I would like to know if you can help me to understand how TI came out with the following values for the PI controllers and the PLL, and why PI controllers instead of PR controller or something else:
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#define TTPLPFC_GI_PI_KP (float) 0.3496503407
#define TTPLPFC_GI_PI_KI (float) 0.0020000510
#define TTPLPFC_GV_PI_KP (float) 0.6004499882
#define TTPLPFC_GV_PI_KI (float) 0.0001000236
.
.
.
SPLL_1PH_SOGI_reset(&TTPLPFC_spll1);
SPLL_1PH_SOGI_config(&TTPLPFC_spll1,
TTPLPFC_AC_FREQ,
TTPLPFC_CONTROL_ISR_FREQUENCY,
(float32_t)(222.2862),
(float32_t)(-222.034));
.
.
.
Any insights on addressing resonance issues in grid-connected power converters, especially regarding controller tuning methods, or SPLL parameter optimization would be greatly appreciated.
I would appreciate any feedback and if you know of any useful literature and/or workshops in the US to learn about digital control implementation.
Best,
Wilson