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TMS320F28P650DK: CMPSS DAC Electrical Characteristics

Johnny Chen
Expert 5090 points
Part Number: TMS320F28P650DK


Tool/software:

Hi Champ,

I am asking for my customer.

They are testing with giving the same DAC value in mulitiple CMPSS modules for PCM control. The I_sense signal is connected to the positive input of CMPSS.

It turned out a severe current unbalancing in multi-phases topology.

(1). The worst case scenario, the static error of DAC static could be as much as 25mV from offset + 66mV from gain (2% of full scale range), right ? Did I miss any parameter ?

Besides, I should also consider the ADC gain error (45 LSB) for causing multi-phases current unbalancing here, right ?

(2). The static offset error can be compensated/calibrated in the software, right ? could the gain error be compensated/calibrated (2% of full scale range) in any way ?

(3). Since customer will also add ramp generator in next step, there is a CMPSS DAC Dynamic Error.

Is the Max. total CMPSS DAC error be 25mV from offset + 66mV from gain + DYNAMICERROR ? could the DAC Dynamic Error be compensated/calibrated in any way ?

Thanks and regards,

Johnny

  • 0
    TI__Expert 4940 points

    - Yes, DAC static error includes offset error (up to ±25 mV) and gain error (±2% which is ±66 mV) in a worst-case. You have to also consider ADC errors (45 LSB ~36 mV).

    - You can consider software-based offset calibration which typically involves taking zero-current readings and adjusting DAC reference accordingly. You can also, measure actual current for a known DAC threshold across phases and then apply scaling correction factors.

    - I suggest to consider the calibration process for CMPSS in TRM “20.6.3 Calibrating the CMPSS”.

    Best Regards,

    Masoud

  • 0 in reply to Masoud Farhadi
    TI__Expert 5090 points

    Hi Masoud,

    Thanks for your prompt input.

    From TRM 20.6.3, customer is having the inverting input of the comparator driven from the compdac, then only the compdac (static) offset error is considered here.

    Masoud Farhadi said:
    You can consider software-based offset calibration which typically involves taking zero-current readings and adjusting DAC reference accordingly. You can also, measure actual current for a known DAC threshold across phases and then apply scaling correction factors.

    Is above software-based offset calibration referring to the calibration process for CMPSS in TRM “20.6.3 Calibrating the CMPSS” ? 

    If not, does user need to do both calibration process mentioned in TRM and also the calibration process ? or either one would be enough to calibrate the CMPSS ? what's the suggestion 

    Masoud Farhadi said:
    I suggest to consider the calibration process for CMPSS in TRM “20.6.3 Calibrating the CMPSS”.

    Customer would like to implement the approach on the EVM first. Is it capable to do with our EVM ?

    Could the expert provide a showcase / example for the calibration approach ?

    Thanks and regards,

    Johnny

  • 0 in reply to Johnny Chen
    TI__Expert 4940 points

    Johnny,

    To handle ADC offset compensation, we usually rely on a routine like the routine found in the C2000 motor control SDK under "Universal motor control" example. Just look for the "runMotor1OffsetsCalculation" function in the "motor1_drive.c" file. As for DAC value compensation, I don't know of any specific examples. The customer can refer to the TRM to learn how to compensate for DAC offset.

    Best Regards,

    Masoud