TMS320F28388S: EMIF connect to FPGA data unstable

Part Number: TMS320F28388S

Tool/software:

Hi Team,

When use below config, it may be encounter some data unstable issue.

    tparam.rSetup = 1;

    tparam.rStrobe = 5;

    tparam.rHold = 1;

    tparam.turnArnd = 0;

    tparam.wSetup = 1;

    tparam.wStrobe = 4;

    tparam.wHold = 2;

    EMIF_setAsyncTimingParams(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, &tparam);

After change config, it can solve data unstable issue, but our DSP maybe dead.

    tparam.rSetup = 3;

    tparam.rStrobe = 7;

    tparam.rHold = 3;

    tparam.turnArnd = 0;

    tparam.wSetup = 3;

    tparam.wStrobe = 7;

    tparam.wHold = 5;

    EMIF_setAsyncTimingParams(EMIF1_BASE, EMIF_ASYNC_CS2_OFFSET, &tparam);

After dsp dead, it can't connect to debuger:

Could you help give us some debug advice, thanks!

Best Regards,

Zane