TMS320F28P650DK: DMA configuration

Hi Ariel,

An issue I see is that the step sizes are set to 0, this means that the src and destination address will remain the same for every burst. The way you have it now, each ADC trigger will cause the top 16-bits of the u32_Ariel_Test_src variable to move over (which is just zero) and it will be moved into the top 16-bits of the u32_Ariel_Test_dest variable, which is why you don't see anything actually updating. With this setup, you would want to change the burst size to 1. You also have the wrap size set to zero which means on top of this it will wrap back to the first address after every burst, which means it will never get to that bottom 16-bits. You should set the wrap size to 65535 if you don't actually want it to wrap.

However, I would suggest using the 32-bit setting if using a 32-bit variable for the DMA to read write. Then both the burst and transfer sizes can be set to 1. In this case it is fine to have a step size of 0 since there is only one burst anyways.

Please upvote this response if it answers your question.

Best Regards,

Delaney

So if I understood correctly: I should leave the the 32bit config and just change the burst size from 2 to 1.

If that is your suggestion - I still don't see any data update.

Hi Ariel,

Can you also change the wrap size (I recommend 65535)? 

If this still doesn't fix it, please send me the status of the CONTROL register in the registers window of CCS (with continuous refresh enabled).

Best Regards,

Delaney

Sadly - still not working.

DmaRegs        DMA Registers    
    DMACTRL    0x0000    DMA Control Register [Memory Mapped]    
    DEBUGCTRL    0x0000    Debug Control Register [Memory Mapped]    
    PRIORITYCTRL1    0x0000    Priority Control 1 Register [Memory Mapped]    
    PRIORITYSTAT    0x0000    Priority Status Register [Memory Mapped]    

Dmach1Regs        DMA CH Registers    
    MODE    0x4901    Mode Register [Memory Mapped]    
    CONTROL    0x0100    Control Register [Memory Mapped]    
    BURST_SIZE    0x0000    Burst Size Register [Memory Mapped]    
    BURST_COUNT    0x0000    Burst Count Register [Memory Mapped]    
    SRC_BURST_STEP    0x0000    Source Burst Step Register [Memory Mapped]    
    DST_BURST_STEP    0x0000    Destination Burst Step Register [Memory Mapped]    
    TRANSFER_SIZE    0x0000    Transfer Size Register [Memory Mapped]    
    TRANSFER_COUNT    0x0000    Transfer Count Register [Memory Mapped]    
    SRC_TRANSFER_STEP    0x0000    Source Transfer Step Register [Memory Mapped]    
    DST_TRANSFER_STEP    0x0000    Destination Transfer Step Register [Memory Mapped]    
    SRC_WRAP_SIZE    0xFFFE    Source Wrap Size Register [Memory Mapped]    
    SRC_WRAP_COUNT    0x0000    Source Wrap Count Register [Memory Mapped]    
    SRC_WRAP_STEP    0x0000    Source Wrap Step Register [Memory Mapped]    
    DST_WRAP_SIZE    0xFFFE    Destination Wrap Size Register [Memory Mapped]    
    DST_WRAP_COUNT    0x0000    Destination Wrap Count Register [Memory Mapped]    
    DST_WRAP_STEP    0x0000    Destination Wrap Step Register [Memory Mapped]    
    SRC_BEG_ADDR_SHADOW    0x000252D2    Source Begin Address Shadow Register [Memory Mapped]    
    SRC_ADDR_SHADOW    0x000252D2    Source Address Shadow Register [Memory Mapped]    
    SRC_BEG_ADDR_ACTIVE    0x00000000    Source Begin Address Active Register [Memory Mapped]    
    SRC_ADDR_ACTIVE    0x00000000    Source Address Active Register [Memory Mapped]    
    DST_BEG_ADDR_SHADOW    0x000252D4    Destination Begin Address Shadow Register [Memory Mapped]    
    DST_ADDR_SHADOW    0x000252D4    Destination Address Shadow Register [Memory Mapped]    
    DST_BEG_ADDR_ACTIVE    0x00000000    Destination Begin Address Active Register [Memory Mapped]    
    DST_ADDR_ACTIVE    0x00000000    Destination Address Active Register [Memory Mapped]    

Hi Ariel,

From your registers, it looks like the trigger is happening, but no data is actually moved over. I also see that the RUN bit in this register is not set (since the 0th bit in the CONTROL register is 0). Can you add a call to DMA_startChannel(DMA_CH1_BASE) at the end of your initializations? Please upvote this reply if that fixes the issue.

Best Regards,

Delaney