• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 82 subscribers
  • Views 158 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F280039-Q1: Why the system clock after the power off and power on

Shuqing Zhou
Intellectual 2285 points
Part Number: TMS320F280039-Q1


Tool/software:

Hi experts,

I ask this for my customer. They use the launchpad and demo: sysctl_ex2_xclkout_config, and they change the output clock is SYSCTL_CLOCKOUT_SYSCLK in GPIO16.

They delete the Device_init(); and load the program and run the code, because they delete the Device_init(), so the system clock is default is 10MHz.

But hey find in this time, the output clock is 15MHz(that means system clock is 120MHz since they set SYSCTL_XCLKOUT_DIV_8 in the code; Then they keep the power but click the CPU reset in CCS and EMU boot to flash and run, the output clock is still 15MHz.

Then they power off and power on and connect the CPU not reload the program, and restart, they find the output clock is 1.25MHz(that means system clock is 10MHz);

They have confused that they don't reload the program, but why the system clock change from 15MHz to 1.25MHz after power cycle?

BRs

Shuqing

  • 0
    TI__Expert 4920 points

    Hello,

    When the device is powered on, it starts with a default clock configuration, which is 10MHz in this case. The Device_init() function is responsible for configuring the device's clocks, including the system clock.

    When customer deletes the Device_init() call and runs the code, the system clock remains at its default value of 10MHz. However, when they configure the SYSCTL_XCLKOUT_DIV_8 and set the output clock to SYSCTL_CLOCKOUT_SYSCLK in GPIO16, they are effectively dividing the system clock by 8 to generate the output clock. Since the system clock is still at 10MHz, the output clock would be 1.25MHz (10MHz / 8).

    However, when they click the CPU reset in CCS and EMU boots to flash and runs, the code is re-executed, and the SysCtl_setXCLKOUT function is called again, which configures the output clock to 15MHz (120MHz / 8). This is why the output clock remains at 15MHz after the CPU reset.

    Now, here's the interesting part: when your customer powers off and powers on the device without reloading the program, the device's clock configuration is lost, and it reverts to its default state. This means that the system clock goes back to 10MHz, and the output clock, which is still configured to SYSCTL_CLOCKOUT_SYSCLK, becomes 1.25MHz (10MHz / 8) again.

    The reason for this behavior is that the TMS320F28x device uses a combination of hardware and software to configure its clocks. The clock configuration is stored in the device's registers, which are volatile and lose their values when the device is powered off. When the device is powered on again, the registers are reset to their default values, and the clock configuration is lost.