TMS320F28386D: Multicore synchronous halt/release support

Hi Zakaria,

Please see the following links:

HW breakpoints:

https://software-dl.ti.com/ccs/esd/documents/users_guide_ccs_20.1.1/gel/hw_brkpt.html 

https://software-dl.ti.com/ccs/esd/documents/ccs_breakpoint_watchpoint_c2000.html 

Cross-triggering information:

https://software-dl.ti.com/ccs/esd/documents/users_guide_ccs_20.1.0/ccs_debug-main.html#breakpoints-multi-core 

Regards,

Ozino

Thanks Ozino,

From the links you shared, my understanding is that the debugger will either use a software or hardware synchronization depending if the SoC supports or not. This what we are trying to confirm, in fact we are not using TI debugger, we are using a similar concept for groups and sync, but we would like to know if there's a hardware support for the cross-trigger. 

From our measurements, the synchronization is not deterministic and it takes a considerable amount of time (in the order of 5ms) which makes us suspect that the synchronization is done by software. 

Can you please confirm ?

Thanks

Hi,

Please refer to this forum post for more information on what is available in software vs hardware on our devices.

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/144230/breakpoints-in-c28x---xds100v2 

Regards,

Ozino

Hi,

This post talks about hardware breakpoints, we are trying to find if there is something like CTI (for ARM) in the TMS320Fxx. We want to know if the grouped halt and release of all cores is synchronized with hardware support, or it's the debugger doing software simulation of it.

Hi,

I will need to reach out to our design team to further assist your question. Please expect a delayed response. Thank you for your patience.

Regards,

Ozino