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TMS320F28379D: Interrupt latency for EPWM ISR

Mark Feller
Expert 1220 points
Part Number: TMS320F28379D

Tool/software:

I have EPWM1A configured to go high on TBCTR=ZERO

With 100MHz SYSCLK and dividers set to /1

I have the ISR configured to trigger at CMPB=10  (for example, I have tried different values).  At CMPB=10, I expect the ISR to be triggered at 0.10us plus some interrupt latency.  

I am seeing something like 5.37us between the rising edge of EPWM1a and a debug pin that I set in the ISR.  I understand there is some interrupt latency between when the interrupt is triggered and when the ISR execution begins, but 5us seems like it may be high.

What type of interrupt latency should I expect on a TBCTR=CMPBU?

A screenshot of the timing and some relevant code snippets are below.

 

EPWM_setClockPrescaler(epwm_data_ptr->epwm_base, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

EPWM_setTimeBaseCounterMode(pc_epwm_ptr->epwm_base, EPWM_COUNTER_MODE_UP);

EPWM_setActionQualifierAction(pc_epwm_ptr->epwm_base,EPWM_AQ_OUTPUT_A,EPWM_AQ_OUTPUT_HIGH,EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
EPWM_setActionQualifierAction(pc_epwm_ptr->epwm_base,EPWM_AQ_OUTPUT_A,EPWM_AQ_OUTPUT_LOW,EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

EPWM_setCounterCompareValue(epwm_data_ptr->epwm_base,EPWM_COUNTER_COMPARE_B, 10); 

EPWM_setInterruptSource(epwm_data_ptr->epwm_base, EPWM_INT_TBCTR_U_CMPB);

__interrupt void epwm1_isr(){

GPIO_writePin(124,1);

EPWM_clearEventTriggerInterruptFlag(EPWM1_BASE);
Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP3);

GPIO_writePin(124,0);

}

I also have deadband enabled, with DBRED=DBFED=40 (Active High Complementary)

  • 0
    TI__Expert 3700 points

    Hello,

    I will take a look and reply in timely manner.

  • 0 in reply to Stevan Duraskovic
    TI__Mastermind 18345 points

    Hi Mark,

    Below is some information about interrupt latency on the C28x in general:

    The steps the CPU goes through when it gets an interrupt are actually as follows:

    The steps take around the below amount of time

    • Clearing the CPU pipeline: ~8 cycles (can be more if CPU is executing a RPT instruction)
    • Context Save: ~8 cycles
    • ISR - x cycles
    • Context Restore: ~8 cycles

    So overall they can expect interrupt overhead to be around 24 cycles (so fairly negligible). 

    Below are some other things they can do to help with tight interrupt timing:

    • Avoid doing (non-inline) function calls inside the ISR. Use direct HWREG accesses to registers
    • Avoid doing any sort of polling/waiting loop inside the ISR - for example don't call a blocking SPI function that will require the CPU to wait
    • Turn compiler optimizations on in the project properties to minimize instructions used
    • Set the HPI compiler pragma for each ISR so that the FPU registers don't need to be pushed onto the stack (this setting saves them in shadow registers instead).
    • Avoid using RPT instruction

    I'll let Stevan comment on interrupt timing from the ePWM perspective.

    Best Regards,

    Delaney

  • 0
    Expert 1220 points

    I found I have an ADC interrupt also triggered by the PWM, that is holding off the PWM ISR.