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TMS320F2800157-Q1: ePWM Interrupt trigger event is missed when duty is 0% means CMPA == TBPRD and INT source is TBCTR == CMPA when incrementing.

Meet Parikh
Prodigy 171 points

Dear TI Experts,

Background:

I am attempting to generate a pulse-skipping scenario by symmetrically enabling and disabling the ePWMA and ePWMB outputs.

ePWM Setup:

  • Counter Mode: Up-Down counting

  • TBPRD = 200

  • CMPA = 0 (Based on duty = 100%)

  • CMPA is loaded at Zero Event (TBCTR == 0)

  • Interrupt Source: CMPA match when TBCTR == CMPA while counting down

Query 1 : what happens when TBCTR == CMPA == ZERO (100% duty scenario)?

Assumption: The CMPA match event will be missed in this case, because at TBCTR == 0, the counter is transitioning from down-counting to up-counting. Therefore, the TBCTR == CMPA == ZERO match does not occur while TBCTR is in the down-count phase.

 Is this assumption valid?

ePWM Setup:

  • Counter Mode: Up-Down counting

  • TBPRD = 200

  • CMPA = 200 (Based on duty 0%)

  • CMPA is loaded at Zero Event (TBCTR == 0)

  • Interrupt Source: CMPA match when TBCTR == CMPA while counting up

Query 2: What happens when TBCTR == CMPA == TBPRD (0% duty scenario)?

Assumption: The CMPA match event will be missed because at TBCTR == CMPA == TBPRD, the counter reverses direction and starts counting down. Therefore, the TBCTR == CMPA condition does not occur while counting up.

 Is this understanding, correct?


Kindly give clarification for the above queries and let us know how to handle 0% and 100% duty when dealing with symmetric PWMs in UP-DOWN count mode.

  • 0
    Prodigy 171 points

    From TRM :

    Up-Down Count Mode: In up-down count mode, the time-base counter starts from zero and increments
    until the period (TBPRD) value is reached. When the period value is reached, the time-base counter then
    decrements.

    For up-down count mode, each event
    occurs twice per cycle if the compare value is between 0x00-TBPRD; and once per cycle if the compare value is
    equal to 0x00 or equal to TBPRD.

    Use up-down count mode to generate a symmetric PWM:
    • If loading CMPA/CMPB on zero, then use CMPA/CMPB values greater than or equal to 1.
    • If loading CMPA/CMPB on period, then use CMPA/CMPB values less than or equal to TBPRD-1.
    This means there is always a pulse of at least one TBCLK cycle in a PWM period which, when very
    short, tend to be ignored by the system.

  • 0 in reply to Meet Parikh
    TI__Mastermind 18345 points

    Hello,

    I have looped in the expert from the team, and they should get back to you with a response in the next 1-2 days.

    Best Regards,

    Delaney

  • +1 in reply to Delaney Woodward
    TI__Mastermind 25446 points

    Hi Meet,

    Query 1 (TBCTR = CMPA = ZERO, 100% duty):
    Your assumption is not entirely correct. When CMPA = 0 in up-down count mode:
    1. The CMPA match event will still occur when TBCTR = 0
    2. The compare match logic checks for equality at ZERO. For AQ action, only action that occurs is when CMPA == ZRO on a counter up event. The event trigger will only fire when CTR = CMPA on ZRO when counter is counting up.


    Query 2 (TBCTR = CMPA = TBPRD, 0% duty):
    Your assumption is also not entirely correct. When CMPA = TBPRD:
    1. The CMPA match event will occur when TBCTR = TBPRD
    2. The compare match logic is implemented to detect the match at the period value
    3. The match event is generated before the counter direction changes from up-counting to down-counting for only the action qualifier. However the event interrupt does not generate an interrupt if the CMPA == TBPRD when timer is incrementing. Only will generate interrupt when CMPA == TBPRD when timer is decrementing.

    Important Notes:
    1. Instead of having to worry about these edge cases, since these are known limitations of the ePWM please refer to the following recommendations. 

    The best practice is to use non zero CMPA/CMPB events and use the zero action or period actions instead for achieving require duty cycle. There are some edge cases where there have been missing pulses on the output based on how fast the CMPx values get updated and what happens on the output.

    If you would like to verify the behavior of query1/2 in your specific application, you can run this example test case that uses CMPA = 0 to generate interrupt + toggle the output. You will see that this works. However, please adhere to the best practice statement.

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/171/Universal-Project.7z

    Best,

    Ryan Ma