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TMS320F28P650DK: MinDB & ICL - what, how and mainly why

ALon G
Prodigy 55 points
Part Number: TMS320F28P650DK

Tool/software:

Dear Experts,

I am trying to achieve a simple guard on a PWM signal but it's not clear how to use these modules.

The (one, and very very basic) available example and video appear to mix and combine the minimum deadband and the ICL functionalities.

Is this for a reason ? is there a mandatory link between these two features ? why is there a third EPWM signal entering the table ? do I have to have a signal there even if I'm not using it?

Suppose all I want to achieve is this basic guard:

If EPWM4A and EPWM4B both equal 1, then output 0 to both 

Do I have to use the MinDB module in this case? do I have to tie some PWM signal to the lookup table and fill it up with duplicate entries so that it is treated as "X"? 

Thank You,

-Alon.

  • 0
    TI__Mastermind 18345 points

    Hello,

    I have looped in the expert from the team, and they should get back to you with a response in the next 1-2 days.

    Best Regards,

    Delaney

  • 0
    TI__Genius 12955 points

    Hi,

    In the example, EPWM4 only applies min deadband without ICL and EPWM5 only applies ICL without any MINDB.

    This is explained in the comments of the examples and shown below so these are independent features and not linked.

    Yes there are three inputs to the ICT look up table, two from same PWM A/B outputs and optionally we can port another pwms o/p through ICL XBAR for look up table which is what the example is showing.

    Look up table is configurable so you can set the LOOK UP TABLE config such that the third input is completely ignored, since each combination in the look up table is user configurable. The third signal is to provide user flexibility to add another pwm instances o/p for look up table. 

    Like 

    | ePWM4A | ePWM4B | third channel | ePWM4A | <-- 4A output
    //!     |--------|--------       |--------           |--------          |
    //!     |    0   |            0   |               X   |         0   |
    //!     |    0   |            1   |               X   |         0   |
    //!     |    1   |            0   |               X   |         0   |
    //!     |    1   |            1   |               X   |         1   |
    //!     |________|________|________|________|

    Thanks