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TMS320F28P650DH: spi_ex5_loopback_dma

nie chunying
Intellectual 350 points
Part Number: TMS320F28P650DH

Tool/software:


Hello, expert. Currently, I am working on the communication of the F28P65 upper computer. The DSP is the SPI slave device, and the upper computer (made by QT) is the master device. Following the process of -spi_ex5_loopback_dma, I rewrote the code. When I debugged the upper computer, it was able to correctly send and receive 180 characters as shown in Figure 1. During the debugging process, the upper computer kept sending and receiving 270 characters, but it encountered an error as shown in Figure 2.

1.Question: If we only need to modify the SPI_DMA to send a fixed number of bytes and receive a fixed number of bytes, what code should be modified?

first

rData[] is the receiving array of SPI_DMA

Figure 1

------------This fixed byte is 180 characters long and the transmission and reception are both correct.

next

The upper computer sends data for the first time, and it enters the DSP receiving interrupt. The data is correct.

rData[] is the receiving array of SPI_DMA

The upper computer sent the data for the second time, but it triggered the DSP's receiving interrupt. The data was incorrect.

The upper computer sent the data for the third time, but it entered the DSP receiving interrupt but the data was incorrect.

2.SPI configuration

Figure 2

3.270-character fixed sending and receiving and 180-character fixed sending and receiving - modification points----The main task is to modify the TRANSFER and BURST data lengths, and also to adjust the lengths of the sending and receiving arrays.

Question: If we only need to modify the SPI_DMA to send a fixed number of bytes and receive a fixed number of bytes, what code should be modified?

Figure3

  • 0
    TI__Genius 15905 points

    Hi Nie,

    These are the relevant configurations to modify for SPI DMA operations.

    Best Regards,

    Aishwarya

  • 0 in reply to Aishwarya Rajesh
    Intellectual 350 points

    Hello, expert. Thank you very much for your reply.

       My question is: First of all, the configuration of sending and receiving 180 characters is correct. From this, it can be seen that I have to configure correctly. Now I want to change the length of the sent data and the length of the received data, but it is not configured correctly. I configured it as shown in the picture. The size of DMA_BURST_SIZE is equal to TX FIFO and RX FIFO. Calculate DMA_TRANSFER_SIZE based on the total bytes to be sent and received.

       I would like to ask what the reason is that the data I received was correct the first time but incorrect the second time? As shown in last time - Figure 3; If I configure it incorrectly, I won't receive it correctly the first time either

  • 0
    TI__Genius 15905 points

    Nie,

    Let me get back to you on this. Thanks.

    Best Regards,

    Aishwarya

  • 0
    TI__Genius 15905 points

    Nie,

    The data at transfers could be misaligned? Could you send a screenshot of the registers for burst / transfer size, etc. And confirm the desired configs? 

    In between transfers, is there data in the RX / TX FIFO? It should be eMott, taken care of in hardware, when not in use.

    Is the DMA being triggered properly and clearing appropriate SPI flags in between transfers? 

    Best Regards,

    Aishwarya 

  • 0 in reply to Aishwarya Rajesh
    Intellectual 350 points

    Hello, expert. Thank you very much for your reply. The host QT-PC software uses the SPI to convert to USB PHY chip. Send -DMA_CH5_BASE; Receive - DMA_CH6_BASE;

    <<<<<Current configuration - DMA fixed transmission of 270-16 bits; Fixed reception of 270-16 bits; DMA reception completion interrupt, DMA transmission completion interrupt.

    <<<<<Currently, when the debugging (QT) host transmits data and the DSP receives the data, there is a problem of garbled characters;
    Debugging phenomenon: (QT) device transmits data. The slave device does not enter the receiving interrupt for the first transmission. (QT) host transmits the second time and the slave device can enter the receiving interrupt.
    However, the receiving phenomenon is different.
    -------- The header of the data packet received by the slave device is correct, but the tail field has 10 data garbled characters;
    -------- The first 10 data of the received data packet are garbled, and then correct data packets are received.

    1.Below is the register configuration of the DSP (slave device) when the host does not send any data.

    DM5

    DMA6

    SPIA

    2.This is the register configuration of the DSP (the slave device) when the host sent the first data of 270-16 bits (540-8 bits).

    DMA5

    DMA6

    spia

    After the normal host sends 540-8 bits, the DSP slave should enter the DMA reception completion interrupt. Analyze the registers and you will know why the DMA reception completion interrupt did not occur.

    3.This is the register configuration of the DSP (from the device) when the host sends the 270-16 bit (540-8 bit) data for the second time.

    This is when the host sends the 270-16-bit (540-8-bit) data for the second time, the DSP (slave device) enters the DMA reception completion interrupt. Normally, the data at the end is always 0x55. As can be seen from the above figure, the last few data in the receiving array of the DSP (slave device) are garbled.

    DMA5

    DMA6

    SPIA

  • 0 in reply to nie chunying
    Intellectual 350 points

    Hello, expert. I have conducted multiple tests these days, modifying SPI_DMA, BURST_SIZE, and TRANSFER_SIZE. I found that sending and receiving 200 16-bit data is correct. When it exceeds 200 bits, there will be incorrect data when the host sends data and the slave receives data. May I ask if you know whether this is a problem with the host or the slave (DSP)? If it's a DSP issue, how should one identify the problem

  • 0
    TI__Genius 15905 points

    Nie,

    Apologies for the delay. Wanted to check in if you have any updates or any other questions? 

    It sounds like there is some DMA synchronization issues between transfers causing the data mismatch. I'd recommend clearing the memory buffers between transfers. Initially, ensure you are disabling DMA channels and clearing FIFO / DMA flags before starting execution. 

    To determine if its an host issue, check to make sure the host is checking to ensure target is ready and timing is correct between transfers. To determine if its a DSP issue, you can check the SPI FIFO and DMA configurations. 

    Best Regards,

    Aishwarya