• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 83 subscribers
  • Views 111 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P650DK: CLB Behavior During Watchdog Reset on TMS320F28P650

ranjith reddy
Prodigy 130 points
Part Number: TMS320F28P650DK


Tool/software:

Hi TI Experts,

I’m working on an application using the TMS320F28P650D, and I’m encountering a situation where a watchdog reset occurs. I would like to understand the effect of the watchdog reset on the CLB (Configurable Logic Block).

My specific questions are:

  1. What happens to the CLB logic/configuration after a watchdog reset?

  2. Is the CLB automatically re-initialized by the boot process, or do we need to manually reconfigure it in the application initialization?

  3. Does the watchdog reset afftects CLB ?

Any insights or documentation references would be greatly appreciated.

Thanks in advance,

Ranjith 

  • 0
    TI__Genius 13565 points

    Hello Ranjith,

    Our CLB expert is out of office until next Monday, please expect a response 1-2 days after they return.

    Best,

    Matt

  • 0 in reply to Matt Kukucka
    TI__Mastermind 28280 points

    Hi Ranjith,

    1. I don't believe this is documented in the TRM, I will try to set up a test case on my side to observe this myself.

    2. What do you mean by boot process? Are you referring to the initialization procedure in the application code? The CLB behavior should be restored after the initialization procedure is repeated.

    3. I'll test whether a device reset wipes the CLB configuration. Either way, I would expect your CLB configuration to be interrupted when the initialization procedure is repeated.

    Thank you,

    Luke

  • 0 in reply to Luke Jones
    TI__Mastermind 28280 points

    Hi Ranjith,

    I discussed this with other CLB experts, the CLB needs to be reinitialized after a watchdog reset since the GLOBAL_EN bit will be cleared. When the GLOBAL_EN bit is cleared the following will occur:

    • Cell logic is reset
    • FSM states are reset
    • AOC is reset
    • Counters are halted
    • HLC is halted
    • Outputs are gated

    Thank you,

    Luke