Other Parts Discussed in Thread: SYSCONFIG, C2000WARE
Tool/software:
Good evening!
I found an issue in SysConfig.
When I configure the clock tree for the TMS230F2838x device and set AUXPLL to 250MHz and derive the CM clock from it with /2 divider, this divider is ignored.
The code in device.c is alwais
//
// Set up CMCLK to use AUXPLL as the clock source and set the
// clock divider to 1.
//
SysCtl_setCMClk(SYSCTL_CMCLKOUT_DIV_1,SYSCTL_SOURCE_AUXPLL);
regardless of the divider setting in SysConfig.
I see the problem is the clock source for CM is AUXPLLRAWCLK, not AUXPLLCLK, which is divided.