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TMDSCNCD28P65X: PI assembly code and ADC sampling times

Andrew Andoh
Prodigy 50 points
Part Number: TMDSCNCD28P65X


Tool/software:

(1)For DCL_PI_C4.asm provided by TI, does the assembly code have parameters for internal limits for both the integrator saturation and controller saturation? Please confirm. I see Umax,Umin but not Imax, Imin so wanted to confirm. Please suggest a way to incorporate the other if one of them it not included

 

Code can be found here:

https://dev.ti.com/tirex/explore/node?node=A__AJ5S9Wnx5HLPlWFQZhq6uw__digital_power_c2000ware_sdk_software_package__5C6SEVO__LATEST&placeholder=true

(2) Also for ADCs, where would you recommend I trigger my  EPWM SOC trigger from? This is important because I am designing a converter. Is it OK to trigger from when TBCTR= PRD or when a compare values is decrementing?

(3) Is it practical to trigger the ADC ISR interrupt and the ADC sample window from the same SOC. I have this set up but ADC ISR is much slower than I expect.

Regards.

  • 0
    TI__Mastermind 38830 points

    Hi Andrew,

    I'll refer you to the digital power team for (1).  For items (2) and (3), please see response below:

    Andrew Andoh said:
    (2) Also for ADCs, where would you recommend I trigger my  EPWM SOC trigger from? This is important because I am designing a converter. Is it OK to trigger from when TBCTR= PRD or when a compare values is decrementing?

    JC: Yes, you can trigger when TBPRD=PRD and you can also compare when decrementing but usually, the EPWM SOC trigger would be determined depending on the sequence of events that transpire when the EPWM counter starts.  If there are no dependencies in your code, then it really does not matter where the SOC is positioned (could be in PRD/2 or anywhere  between ctr=0 to ctr=PRD).

    Andrew Andoh said:
    (3) Is it practical to trigger the ADC ISR interrupt and the ADC sample window from the same SOC. I have this set up but ADC ISR is much slower than I expect.

    JC: Would you clarify what you mean by triggering ADC sample window and ADC ISR interrupt from the same SOC?  Not sure I am following that.  ADC ISR can be activated at the end of SOC conversion.  For example ADCA SOC0CTL setting is using ADCA channel 5.  If register ADCINTSEL1N2.INT1SEL value is 0, this means that after SOC0 (which is channel 5) finishes conversion, ADCINT1 (ADC interrupt 1) gets set.  When configured, ADCINT1 will trigger an ISR.

    Regards,

    Joseph

  • 0 in reply to Joseph Casuga
    TI__Intellectual 2266 points

    Hi Andrew,

    For Q1, DCL_PI_C4 is the assembly version of the parallel configuration PI controller. It only has the controller saturation (Umin, Umax). Imin and Imax is not used as a parameter. Please see DCL_PI_C3 in DCLF32.h for its equivalent C implementation on what it does.

    Imin and Imax is only used in DCL_PI_C5, the parallel configuration PI with enhanced anti-windup logic where it includes an addintional intergator saturation. DCL_PI_C5 is in C-source and we don't have an assembly equivalent version of it.

    Best,

    Sen Wang

  • 0 in reply to Sen Wang
    Prodigy 50 points

    Thanks for the update. Regarding the integrator limits, what was the process for determining those. I see the sensed variables are scaled [-1,1] and setpoint [0,1] in most TI sample codes but for some integrator limits I see [-1,1] as integrator limits and [-5,5] etc. How were those integrator values figured out?

  • 0 in reply to Andrew Andoh
    TI__Intellectual 2266 points

    Hi Andrew,

    The integrator limits (Imin, Imax for DCL_PI_C5) depends on what's your acceptable ranges of output/control effort. Since our controllers are unit-less, the output units and ranges depends on what your input is.

    Most of TI reference design example uses pu (per-unit), and therefore output efforts (uk) at most would be in the ranges of [-1,1] (Umin, Umax). And you get to pick the integrator limit within these ranges, when integrator exceeds the ranges you pick, it'll disable the integrator feedback path for the next calculation. 

    Although if your Umin/Umax output ranges are in [-1,1], then setting a Imin/Imax integrator limit of [-1,1] essentially doesn't do anything, since the feedback loop would already be disabled by the controller saturation clamp. Imin/Imax are meant to provide a granular control by disabling integrator feedback path before the complete feedback saturation clamp kicks in.  (i.e Imax or Imin are meaningless if abs(Imax) >= abs(Umax) or abs(Imin) >= abs(Umin))

    Best,

    Sen Wang