How to reset Ethernet PHY with Concerto MII

Since the "direction" mode is "hardware", it seems to me that there should be some API or EMAC register that controls it, but I can't find any such thing.

Hi Will,

sorry for the delay, we are looking into it. Did you try any other GPIO muxing option for the PHYRSTn PIN?

Best Regards

Santosh

I have M_MIIPHYRST assigned to PH0_GPIO48 (Pin#41) on my board, which is different from the ControlCard dev kit.

But I don't think that's the problem because I've probed the MIIPHYRST signal on the ControlCard and it doesn't toggle either.

Jason Qian at TI has corroborated my finding that the LWIP example's reset function only resets the onboard peripheral, but does not seem to affect the MIIPHYRST output pin.

Thanks,
-Will 

Will,

Is your PHY chip's reset pin active high or active low?

The MIIPHYRSTn output is high in the non-reset state, so it worked fine with the Concerto control card, which has an active-low reset. I don't think we tested it with an active high reset for the external PHY.

Configuring the pin as GPIO should work as a temporary solution.

We are looking into why the output isn't changing when resetting the ethernet peripheral.

Regards,

Alvaro

Alvaro,

My PHY's reset is active-low, just like the PHY on the ControlCard.

Thanks for investigating.
-Will 

Will,

can you check if your PHY can be reset by writing to the MR0 register using MAC CTRL registers?

Best Regards

santosh

Hi Will,

After examine your program. It seems you have mapped MIIPHYRST to PJ7_GPIO63 instead of PH0_GPIO48. That's why you don't see the toggling of PH0_GPIO48. You can either connect the reset pin to GPIO63 or you have to modify your program to map the MIIPHYRST to PH0_GPIO48 instead. Let me know if that solves the issue.

Hi Jason,

MII_PHYRSTn peripheral function can be configured either on PJ7_GPIO63 or on PH0_GPIO48 among other GPIO Muxing options.

Whatever is mentioned by Alvaro, is right. In this revision of Silicon MII_PHYRSTn doesn;t reset PHY whenever EMAC controller is reset. We are going to errata the behavior and the workaround here is to configure the pin as a GPIO and toggle it before resetting the EMAC controller - as mentioned by Alvaro above.

Best Regards
Santosh

Hi Santosh,

Thanks for the clarification. If this design issue is related to software please advice when is the next API release. If this is a hardware issue please advice when is the next silicon revision.

I have changed the pin formerly configured as M_MIIPHYRST to GPIO (GPIO48 on my board).  I assert it (active-low) before the EMAC reset function, and release it afterward.  This causes a 17.6uS negative pulse and allows my PHY chip to boot properly.

Thanks for all your help.

In Concerto_IO_Config.h:

   #define MIIPHYRST_PORT_BASE            GPIO_PORTH_BASE
   #define MIIPHYRST_PORT_OFFSET       GPIO_PIN_0

   /* Activate reset of the external ethernet PHY chip.  Active Low */
   #define MIIPHYRST_ACTIVE                    GPIOPinWrite(MIIPHYRST_PORT_BASE, MIIPHYRST_PORT_OFFSET, 0);

   /* Release reset of the external ethernet PHY chip.  Active Low */
   #define MIIPHYRST_RELEASE                GPIOPinWrite(MIIPHYRST_PORT_BASE, MIIPHYRST_PORT_OFFSET, 1);

In enet_lwip.c:

      MIIPHYRST_ACTIVE;  
      SysCtlPeripheralReset(SYSCTL_PERIPH_ETH);       // Reset the Ethernet Controller registers.
      MIIPHYRST_RELEASE;