TMS320F28388D: Rationale behind setting MCANCLKDIVSEL to 3 in the MCAN External Loopback example for M4

Hi Joseph,

Apologies for the delayed response.

In the case of F2838x, the MCAN module clock frequency is 100 MHz. For the recommendation of 20 MHz, would not a MCANCLKDIVSEL value of 4 be more appropriate(100/(4+1) = 20)? Is it right to expect that any MCANCLKDIVSEL value which ensures MCAN clock is in the 20MHz to 80 MHz range is good enough?

Regards,

Ganesh

Hi Ganesh,

Still not sure where the 100MHz is from.  Maybe you are referring to the system clock (SYSCLK) of the entire chip.  For F28388, the examples are usually configured to run the SYSCLK at the maximum device speed, which is at 200MHz.  The SYSCLK is prescaled before going to the MCAN block and this is done by assigning the appropriate value to MCANCLKDIVSEL so that MCANCLK = SYSCLK/(MCANCLKDIVSEL+1), and yes you want to target MCAN clock to be from 20MHz to 80MHz.

Regards,

Joseph

Hi Joseph,

Apologies for the delayed response. As I had mentioned in the question, we are using the Cortex-M4 core( Connectivity Manager/CM). The clocking for it is as follows:

On using AUXPLL, max CM CLK frequency of 125 MHz is achieved. We are using the SYSPLL and dividing it to operate at CM CLK of 100 MHz.MCAN module is accesible from the CM side as well. The MCANCLKDIVSEL for this is set from CPU1. Based on what you have said, the requirement is 20MHz < MCANCLK < 80MHz. By "recommendation is to have the MCAN have an access to 20MHz, 40MHz and 80MHz" do you mean post division the MCANCLK is recommended to have either of the three recommended values? If yes, would not a MCANCLKDIVSEL value of 4 (100/(4+1) = 20) be the only one which satisfies the recommendation?

Regards,
Ganesh

Hi Ganesh,

So you can also use MCANCLKDIVSEL of 1, 2, 3 and 4 for 100MHz CM CLK to produce MCANCLK from 20MHz to 50MHz.  For 120MHz (or 125MHz) CM CLK, you can use MCANCLKDIVSEL of 1, 2, 3, 4 and 5 to produce MCANCLK from 20MHz to 60MHz.

Regards,

Joseph