Part Number: TMS320F280039C
Other Parts Discussed in Thread: C2000WARE
Tool/software:
Problem phenomenon: Thfe SCL frequency of I2C module is smaller than expected. The I2C Module is 10MHz. From the test data, the total time is 0.1us longer than 10MHz. The configuration of the reference manual is verified. The signal frequency is 1/(2.5us+0.1us)=79.37khz at 80kHz and 1/(12.5us+0.1us)=384.62khz at 400kHz.
[figure below] configure the parameter of I2C clock frequency of 80kHz
[figure below] the measured value is 79.37khz when the I2C clock frequency is 80kHz
[figure below] configure the parameter of I2C clock frequency of 400kHz
[figure below] the measured value is 384.62khz when the I2C clock frequency is 400kHz
Consulting questions:
1. The I2C clock frequency is smaller than expected, which is normal, right?
2. For this phenomenon, you can change the parameter configuration to make the I2C clock frequency meet the expectation. When changing to the actual 400kHz, it actually corresponds to the 417khz configuration in the manual, which exceeds the limit of the maximum I2C clock frequency of 400kHz described in the manual. Can you use it like this?
[figure below] configure the parameter that the actual I2C clock frequency is 400kHz
[figure below] the measured I2C clock frequency is 400kHz
In particular, I changed the I2C clock frequency for testing, and the deviation was even greater at 8MHz and 12Mhz. I want to confirm whether this phenomenon is normal? I'm afraid I haven't configured it properly, but I didn't find any problems after reading the manual carefully.
Test routine path: \ti\c2000\C2000Ware_5_02_00_00\driverlib\f28003x\examples\i2c\i2c_ex2_eeprom.c
In addition, the three parameters involved in the calculation of SCL signal frequency have been given in my post. Take the configuration of I2C module clock 10MHz and SCL signal frequency 400kHz as an example: i2caregs.i2cpsc.all is 11, i2caregs.i2cclkl is 8, and i2caregs.i2cclkh is 7, then the theoretical SCL signal frequency is 120 MHz / {(IPSC + 1) [(ICCL + 5) + (ICCH + 5)]} = 120MHz / {(11 + 1) / [(8 + 5) + (7 + 5)] = 400kHz。
