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Original question:

TMS320F28375D: HRPWM in up-down mode duty control both edge

TMS320F28375D: Relationship between CMPAHR, CMPBHR and jitter

O.H
Mastermind 6720 points
Part Number: TMS320F28375D


Tool/software:

Hi experts,

Please confirm the following points from this thread.

You cannot use CMPAHR and CMBHR for single EPMW output like EPMWA on Type-4 ePWM. CMPAHR is assigned for EPWMA, and EPWMB is assigned for CMBPHR. Setting CMPAHR and CMPBHR to be equal give same effect as setting and clearing solely on CMPAHR. 

Q: Am I correct in understanding the following two points?

  1. The above condition applies only when "Frequency Hi-Res" and "Compare Match Hi-Res" are used in combination.
  2. In the case of "Compare Match Hi-Res", the values ​​of CMPAHR and CMPBHR can be reflected in EPWMA.
    "Frequency Hi-Res" refers to setting "HRPCTL.bit.HRPE=1" and using TBPHSHR.
    "Compare Match Hi-Res" refers to using CMPAHR/CMPBHR.

My customer has a concern when using "Frequency Hi-Res" and "Compare Match Hi-Res" in combination to output a PWM waveform from EPWMA, which led to the above question.

  1. If the TBPHSHR register is set to 0 and different values ​​are entered into the CMPA/CMPB and CMPAHR/CMPBHR registers... no jitter occurs at the rising or falling edges of the pulse.
  2. If the HRPE bit of the HRPCTL register is set to 0, an arbitrary value is set into the TBPHSHR register, and different values ​​are entered into the CMPA/CMPB and CMPAHR/CMPBHR registers... no jitter occurs at the rising or falling edges of the pulse.
  3. Set AQCTLA.bit.ZRO to AQ_SET (or AQ_CLEAR), CMPBHR=0... jitter occurs on the CMPB side at the rising and falling edges.
  4. Set AQCTLA.bit.CBU to AQ_SET (or AQ_CLEAR), CMPBHR=0, and an arbitrary value (other than TBCNT=0-3 and TBPRD-TBPRD-3) is entered into CMPB... jitter occurs.
    → Why does jitter occur?
  5. Set arbitrary values ​​to CMPA and CMPHR... no jitter occurs on the CMPA side.
    4. If you enter arbitrary values ​​into CMPA and CMPB and set CMPAHR and CMPBHR to 0, no jitter occurs on the CMPB side.
    →They believe that this is not

Please let us know if there is any information missing or if you have any questions.

Best regards,
O.H

  • 0
    TI__Expert 5040 points

    Hello,

    I will take a look and reply in timely manner.

  • 0 in reply to Stevan Duraskovic
    Mastermind 6720 points

    Hello,

    Thank you for your support.

    As the customer is currently working on software evaluation using a prototype board, we would appreciate it if you could provide information by the end of this week.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Expert 5040 points

    Hello,

    You cannot apply CMPAHR and CMPBHR to single EPWM output (i.e EPWMA). CMPAHR corresponds to EPWMA and CMPBHR corresponds to EPWMB output. Any other combination would cause you jitter.

    When high-resolution period control is enabled, on ePWMxA only, and not ePWMxB output and conversely, the non high-resolution output has ±1 TBCLK cycle jitter in up-count mode and ±2 TBCLK cycle jitter in up-down count mode.

    For TBPHS:TBPHSHR synchronization with high-resolution period, set both HRPCTL[TBPSHRLOADE] = 1 and TBCTL[PHSEN] = 1. In up-down count mode these bits must be set to 1 regardless of the contents of TBPHSHR even if TBPHSHR = 0x0000. Hope this helps.